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Marc Zyngier021f6532014-06-30 16:01:31 +01001/*
Marc Zyngier0edc23e2016-12-19 17:01:52 +00002 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
Marc Zyngier021f6532014-06-30 16:01:31 +01003 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
Julien Grall68628bb2016-04-11 16:32:55 +010018#define pr_fmt(fmt) "GICv3: " fmt
19
Tomasz Nowickiffa7d612016-01-19 14:11:15 +010020#include <linux/acpi.h>
Marc Zyngier021f6532014-06-30 16:01:31 +010021#include <linux/cpu.h>
Sudeep Holla3708d522014-08-26 16:03:35 +010022#include <linux/cpu_pm.h>
Marc Zyngier021f6532014-06-30 16:01:31 +010023#include <linux/delay.h>
24#include <linux/interrupt.h>
Tomasz Nowickiffa7d612016-01-19 14:11:15 +010025#include <linux/irqdomain.h>
Marc Zyngier021f6532014-06-30 16:01:31 +010026#include <linux/of.h>
27#include <linux/of_address.h>
28#include <linux/of_irq.h>
29#include <linux/percpu.h>
30#include <linux/slab.h>
31
Joel Porquet41a83e062015-07-07 17:11:46 -040032#include <linux/irqchip.h>
Julien Grall1839e572016-04-11 16:32:57 +010033#include <linux/irqchip/arm-gic-common.h>
Marc Zyngier021f6532014-06-30 16:01:31 +010034#include <linux/irqchip/arm-gic-v3.h>
Marc Zyngiere3825ba2016-04-11 09:57:54 +010035#include <linux/irqchip/irq-partition-percpu.h>
Marc Zyngier021f6532014-06-30 16:01:31 +010036
37#include <asm/cputype.h>
38#include <asm/exception.h>
39#include <asm/smp_plat.h>
Marc Zyngier0b6a3da2015-08-26 17:00:42 +010040#include <asm/virt.h>
Marc Zyngier021f6532014-06-30 16:01:31 +010041
42#include "irq-gic-common.h"
Marc Zyngier021f6532014-06-30 16:01:31 +010043
Marc Zyngierf5c14342014-11-24 14:35:10 +000044struct redist_region {
45 void __iomem *redist_base;
46 phys_addr_t phys_base;
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +010047 bool single_redist;
Marc Zyngierf5c14342014-11-24 14:35:10 +000048};
49
Marc Zyngier021f6532014-06-30 16:01:31 +010050struct gic_chip_data {
Marc Zyngiere3825ba2016-04-11 09:57:54 +010051 struct fwnode_handle *fwnode;
Marc Zyngier021f6532014-06-30 16:01:31 +010052 void __iomem *dist_base;
Marc Zyngierf5c14342014-11-24 14:35:10 +000053 struct redist_region *redist_regions;
54 struct rdists rdists;
Marc Zyngier021f6532014-06-30 16:01:31 +010055 struct irq_domain *domain;
56 u64 redist_stride;
Marc Zyngierf5c14342014-11-24 14:35:10 +000057 u32 nr_redist_regions;
Shanker Donthinenieda0d042017-10-06 10:24:00 -050058 bool has_rss;
Marc Zyngier021f6532014-06-30 16:01:31 +010059 unsigned int irq_nr;
Marc Zyngiere3825ba2016-04-11 09:57:54 +010060 struct partition_desc *ppi_descs[16];
Marc Zyngier021f6532014-06-30 16:01:31 +010061};
62
63static struct gic_chip_data gic_data __read_mostly;
Marc Zyngier0b6a3da2015-08-26 17:00:42 +010064static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
Marc Zyngier021f6532014-06-30 16:01:31 +010065
Julien Grall1839e572016-04-11 16:32:57 +010066static struct gic_kvm_info gic_v3_kvm_info;
Shanker Donthinenieda0d042017-10-06 10:24:00 -050067static DEFINE_PER_CPU(bool, has_rss);
Julien Grall1839e572016-04-11 16:32:57 +010068
Shanker Donthinenieda0d042017-10-06 10:24:00 -050069#define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4)
Marc Zyngierf5c14342014-11-24 14:35:10 +000070#define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist))
71#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
Marc Zyngier021f6532014-06-30 16:01:31 +010072#define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
73
74/* Our default, arbitrary priority value. Linux only uses one anyway. */
75#define DEFAULT_PMR_VALUE 0xf0
76
77static inline unsigned int gic_irq(struct irq_data *d)
78{
79 return d->hwirq;
80}
81
82static inline int gic_irq_in_rdist(struct irq_data *d)
83{
84 return gic_irq(d) < 32;
85}
86
87static inline void __iomem *gic_dist_base(struct irq_data *d)
88{
89 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */
90 return gic_data_rdist_sgi_base();
91
92 if (d->hwirq <= 1023) /* SPI -> dist_base */
93 return gic_data.dist_base;
94
Marc Zyngier021f6532014-06-30 16:01:31 +010095 return NULL;
96}
97
98static void gic_do_wait_for_rwp(void __iomem *base)
99{
100 u32 count = 1000000; /* 1s! */
101
102 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
103 count--;
104 if (!count) {
105 pr_err_ratelimited("RWP timeout, gone fishing\n");
106 return;
107 }
108 cpu_relax();
109 udelay(1);
110 };
111}
112
113/* Wait for completion of a distributor change */
114static void gic_dist_wait_for_rwp(void)
115{
116 gic_do_wait_for_rwp(gic_data.dist_base);
117}
118
119/* Wait for completion of a redistributor change */
120static void gic_redist_wait_for_rwp(void)
121{
122 gic_do_wait_for_rwp(gic_data_rdist_rd_base());
123}
124
Jean-Philippe Brucker7936e912015-10-01 13:47:14 +0100125#ifdef CONFIG_ARM64
Robert Richter6d4e11c2015-09-21 22:58:35 +0200126
127static u64 __maybe_unused gic_read_iar(void)
128{
Suzuki K Poulosea4023f682016-11-08 13:56:20 +0000129 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154))
Robert Richter6d4e11c2015-09-21 22:58:35 +0200130 return gic_read_iar_cavium_thunderx();
131 else
132 return gic_read_iar_common();
133}
Jean-Philippe Brucker7936e912015-10-01 13:47:14 +0100134#endif
Marc Zyngier021f6532014-06-30 16:01:31 +0100135
Sudeep Hollaa2c22512014-08-26 16:03:34 +0100136static void gic_enable_redist(bool enable)
Marc Zyngier021f6532014-06-30 16:01:31 +0100137{
138 void __iomem *rbase;
139 u32 count = 1000000; /* 1s! */
140 u32 val;
141
142 rbase = gic_data_rdist_rd_base();
143
Marc Zyngier021f6532014-06-30 16:01:31 +0100144 val = readl_relaxed(rbase + GICR_WAKER);
Sudeep Hollaa2c22512014-08-26 16:03:34 +0100145 if (enable)
146 /* Wake up this CPU redistributor */
147 val &= ~GICR_WAKER_ProcessorSleep;
148 else
149 val |= GICR_WAKER_ProcessorSleep;
Marc Zyngier021f6532014-06-30 16:01:31 +0100150 writel_relaxed(val, rbase + GICR_WAKER);
151
Sudeep Hollaa2c22512014-08-26 16:03:34 +0100152 if (!enable) { /* Check that GICR_WAKER is writeable */
153 val = readl_relaxed(rbase + GICR_WAKER);
154 if (!(val & GICR_WAKER_ProcessorSleep))
155 return; /* No PM support in this redistributor */
156 }
157
Dan Carpenterd102eb52016-10-14 10:26:21 +0300158 while (--count) {
Sudeep Hollaa2c22512014-08-26 16:03:34 +0100159 val = readl_relaxed(rbase + GICR_WAKER);
Andrew Jonescf1d9d12016-05-11 21:23:17 +0200160 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep))
Sudeep Hollaa2c22512014-08-26 16:03:34 +0100161 break;
Marc Zyngier021f6532014-06-30 16:01:31 +0100162 cpu_relax();
163 udelay(1);
164 };
Sudeep Hollaa2c22512014-08-26 16:03:34 +0100165 if (!count)
166 pr_err_ratelimited("redistributor failed to %s...\n",
167 enable ? "wakeup" : "sleep");
Marc Zyngier021f6532014-06-30 16:01:31 +0100168}
169
170/*
171 * Routines to disable, enable, EOI and route interrupts
172 */
Marc Zyngierb594c6e2015-03-18 11:01:24 +0000173static int gic_peek_irq(struct irq_data *d, u32 offset)
174{
175 u32 mask = 1 << (gic_irq(d) % 32);
176 void __iomem *base;
177
178 if (gic_irq_in_rdist(d))
179 base = gic_data_rdist_sgi_base();
180 else
181 base = gic_data.dist_base;
182
183 return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
184}
185
Marc Zyngier021f6532014-06-30 16:01:31 +0100186static void gic_poke_irq(struct irq_data *d, u32 offset)
187{
188 u32 mask = 1 << (gic_irq(d) % 32);
189 void (*rwp_wait)(void);
190 void __iomem *base;
191
192 if (gic_irq_in_rdist(d)) {
193 base = gic_data_rdist_sgi_base();
194 rwp_wait = gic_redist_wait_for_rwp;
195 } else {
196 base = gic_data.dist_base;
197 rwp_wait = gic_dist_wait_for_rwp;
198 }
199
200 writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4);
201 rwp_wait();
202}
203
Marc Zyngier021f6532014-06-30 16:01:31 +0100204static void gic_mask_irq(struct irq_data *d)
205{
206 gic_poke_irq(d, GICD_ICENABLER);
207}
208
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100209static void gic_eoimode1_mask_irq(struct irq_data *d)
210{
211 gic_mask_irq(d);
Marc Zyngier530bf352015-08-26 17:00:43 +0100212 /*
213 * When masking a forwarded interrupt, make sure it is
214 * deactivated as well.
215 *
216 * This ensures that an interrupt that is getting
217 * disabled/masked will not get "stuck", because there is
218 * noone to deactivate it (guest is being terminated).
219 */
Thomas Gleixner4df7f542015-09-15 13:19:16 +0200220 if (irqd_is_forwarded_to_vcpu(d))
Marc Zyngier530bf352015-08-26 17:00:43 +0100221 gic_poke_irq(d, GICD_ICACTIVER);
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100222}
223
Marc Zyngier021f6532014-06-30 16:01:31 +0100224static void gic_unmask_irq(struct irq_data *d)
225{
226 gic_poke_irq(d, GICD_ISENABLER);
227}
228
Marc Zyngierb594c6e2015-03-18 11:01:24 +0000229static int gic_irq_set_irqchip_state(struct irq_data *d,
230 enum irqchip_irq_state which, bool val)
231{
232 u32 reg;
233
234 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
235 return -EINVAL;
236
237 switch (which) {
238 case IRQCHIP_STATE_PENDING:
239 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
240 break;
241
242 case IRQCHIP_STATE_ACTIVE:
243 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
244 break;
245
246 case IRQCHIP_STATE_MASKED:
247 reg = val ? GICD_ICENABLER : GICD_ISENABLER;
248 break;
249
250 default:
251 return -EINVAL;
252 }
253
254 gic_poke_irq(d, reg);
255 return 0;
256}
257
258static int gic_irq_get_irqchip_state(struct irq_data *d,
259 enum irqchip_irq_state which, bool *val)
260{
261 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
262 return -EINVAL;
263
264 switch (which) {
265 case IRQCHIP_STATE_PENDING:
266 *val = gic_peek_irq(d, GICD_ISPENDR);
267 break;
268
269 case IRQCHIP_STATE_ACTIVE:
270 *val = gic_peek_irq(d, GICD_ISACTIVER);
271 break;
272
273 case IRQCHIP_STATE_MASKED:
274 *val = !gic_peek_irq(d, GICD_ISENABLER);
275 break;
276
277 default:
278 return -EINVAL;
279 }
280
281 return 0;
282}
283
Marc Zyngier021f6532014-06-30 16:01:31 +0100284static void gic_eoi_irq(struct irq_data *d)
285{
286 gic_write_eoir(gic_irq(d));
287}
288
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100289static void gic_eoimode1_eoi_irq(struct irq_data *d)
290{
291 /*
Marc Zyngier530bf352015-08-26 17:00:43 +0100292 * No need to deactivate an LPI, or an interrupt that
293 * is is getting forwarded to a vcpu.
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100294 */
Thomas Gleixner4df7f542015-09-15 13:19:16 +0200295 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100296 return;
297 gic_write_dir(gic_irq(d));
298}
299
Marc Zyngier021f6532014-06-30 16:01:31 +0100300static int gic_set_type(struct irq_data *d, unsigned int type)
301{
302 unsigned int irq = gic_irq(d);
303 void (*rwp_wait)(void);
304 void __iomem *base;
305
306 /* Interrupt configuration for SGIs can't be changed */
307 if (irq < 16)
308 return -EINVAL;
309
Liviu Dudaufb7e7de2015-01-20 16:52:59 +0000310 /* SPIs have restrictions on the supported types */
311 if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
312 type != IRQ_TYPE_EDGE_RISING)
Marc Zyngier021f6532014-06-30 16:01:31 +0100313 return -EINVAL;
314
315 if (gic_irq_in_rdist(d)) {
316 base = gic_data_rdist_sgi_base();
317 rwp_wait = gic_redist_wait_for_rwp;
318 } else {
319 base = gic_data.dist_base;
320 rwp_wait = gic_dist_wait_for_rwp;
321 }
322
Liviu Dudaufb7e7de2015-01-20 16:52:59 +0000323 return gic_configure_irq(irq, type, base, rwp_wait);
Marc Zyngier021f6532014-06-30 16:01:31 +0100324}
325
Marc Zyngier530bf352015-08-26 17:00:43 +0100326static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
327{
Thomas Gleixner4df7f542015-09-15 13:19:16 +0200328 if (vcpu)
329 irqd_set_forwarded_to_vcpu(d);
330 else
331 irqd_clr_forwarded_to_vcpu(d);
Marc Zyngier530bf352015-08-26 17:00:43 +0100332 return 0;
333}
334
Jean-Philippe Bruckerf6c86a42015-10-01 13:47:15 +0100335static u64 gic_mpidr_to_affinity(unsigned long mpidr)
Marc Zyngier021f6532014-06-30 16:01:31 +0100336{
337 u64 aff;
338
Jean-Philippe Bruckerf6c86a42015-10-01 13:47:15 +0100339 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
Marc Zyngier021f6532014-06-30 16:01:31 +0100340 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
341 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
342 MPIDR_AFFINITY_LEVEL(mpidr, 0));
343
344 return aff;
345}
346
347static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
348{
Jean-Philippe Bruckerf6c86a42015-10-01 13:47:15 +0100349 u32 irqnr;
Marc Zyngier021f6532014-06-30 16:01:31 +0100350
351 do {
352 irqnr = gic_read_iar();
353
Marc Zyngierda33f312014-11-24 14:35:18 +0000354 if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) {
Marc Zyngierebc6de02014-08-26 11:03:33 +0100355 int err;
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100356
357 if (static_key_true(&supports_deactivate))
358 gic_write_eoir(irqnr);
Will Deacon39a06b62017-07-18 18:37:55 +0100359 else
360 isb();
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100361
Marc Zyngierebc6de02014-08-26 11:03:33 +0100362 err = handle_domain_irq(gic_data.domain, irqnr, regs);
363 if (err) {
Marc Zyngierda33f312014-11-24 14:35:18 +0000364 WARN_ONCE(true, "Unexpected interrupt received!\n");
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100365 if (static_key_true(&supports_deactivate)) {
366 if (irqnr < 8192)
367 gic_write_dir(irqnr);
368 } else {
369 gic_write_eoir(irqnr);
370 }
Marc Zyngier021f6532014-06-30 16:01:31 +0100371 }
Marc Zyngierebc6de02014-08-26 11:03:33 +0100372 continue;
Marc Zyngier021f6532014-06-30 16:01:31 +0100373 }
374 if (irqnr < 16) {
375 gic_write_eoir(irqnr);
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100376 if (static_key_true(&supports_deactivate))
377 gic_write_dir(irqnr);
Marc Zyngier021f6532014-06-30 16:01:31 +0100378#ifdef CONFIG_SMP
Will Deaconf86c4fb2016-04-26 12:00:00 +0100379 /*
380 * Unlike GICv2, we don't need an smp_rmb() here.
381 * The control dependency from gic_read_iar to
382 * the ISB in gic_write_eoir is enough to ensure
383 * that any shared data read by handle_IPI will
384 * be read after the ACK.
385 */
Marc Zyngier021f6532014-06-30 16:01:31 +0100386 handle_IPI(irqnr, regs);
387#else
388 WARN_ONCE(true, "Unexpected SGI received!\n");
389#endif
390 continue;
391 }
392 } while (irqnr != ICC_IAR1_EL1_SPURIOUS);
393}
394
395static void __init gic_dist_init(void)
396{
397 unsigned int i;
398 u64 affinity;
399 void __iomem *base = gic_data.dist_base;
400
401 /* Disable the distributor */
402 writel_relaxed(0, base + GICD_CTLR);
403 gic_dist_wait_for_rwp();
404
Marc Zyngier7c9b9732016-05-06 19:41:56 +0100405 /*
406 * Configure SPIs as non-secure Group-1. This will only matter
407 * if the GIC only has a single security state. This will not
408 * do the right thing if the kernel is running in secure mode,
409 * but that's not the intended use case anyway.
410 */
411 for (i = 32; i < gic_data.irq_nr; i += 32)
412 writel_relaxed(~0, base + GICD_IGROUPR + i / 8);
413
Marc Zyngier021f6532014-06-30 16:01:31 +0100414 gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);
415
416 /* Enable distributor with ARE, Group1 */
417 writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
418 base + GICD_CTLR);
419
420 /*
421 * Set all global interrupts to the boot CPU only. ARE must be
422 * enabled.
423 */
424 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
425 for (i = 32; i < gic_data.irq_nr; i++)
Jean-Philippe Brucker72c97122015-10-01 13:47:16 +0100426 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
Marc Zyngier021f6532014-06-30 16:01:31 +0100427}
428
Marc Zyngier0d94ded2016-12-19 17:00:38 +0000429static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *))
Marc Zyngier021f6532014-06-30 16:01:31 +0100430{
Marc Zyngier0d94ded2016-12-19 17:00:38 +0000431 int ret = -ENODEV;
Marc Zyngier021f6532014-06-30 16:01:31 +0100432 int i;
433
Marc Zyngierf5c14342014-11-24 14:35:10 +0000434 for (i = 0; i < gic_data.nr_redist_regions; i++) {
435 void __iomem *ptr = gic_data.redist_regions[i].redist_base;
Marc Zyngier0d94ded2016-12-19 17:00:38 +0000436 u64 typer;
Marc Zyngier021f6532014-06-30 16:01:31 +0100437 u32 reg;
438
439 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
440 if (reg != GIC_PIDR2_ARCH_GICv3 &&
441 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
442 pr_warn("No redistributor present @%p\n", ptr);
443 break;
444 }
445
446 do {
Jean-Philippe Brucker72c97122015-10-01 13:47:16 +0100447 typer = gic_read_typer(ptr + GICR_TYPER);
Marc Zyngier0d94ded2016-12-19 17:00:38 +0000448 ret = fn(gic_data.redist_regions + i, ptr);
449 if (!ret)
Marc Zyngier021f6532014-06-30 16:01:31 +0100450 return 0;
Marc Zyngier021f6532014-06-30 16:01:31 +0100451
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +0100452 if (gic_data.redist_regions[i].single_redist)
453 break;
454
Marc Zyngier021f6532014-06-30 16:01:31 +0100455 if (gic_data.redist_stride) {
456 ptr += gic_data.redist_stride;
457 } else {
458 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
459 if (typer & GICR_TYPER_VLPIS)
460 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
461 }
462 } while (!(typer & GICR_TYPER_LAST));
463 }
464
Marc Zyngier0d94ded2016-12-19 17:00:38 +0000465 return ret ? -ENODEV : 0;
466}
467
468static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr)
469{
470 unsigned long mpidr = cpu_logical_map(smp_processor_id());
471 u64 typer;
472 u32 aff;
473
474 /*
475 * Convert affinity to a 32bit value that can be matched to
476 * GICR_TYPER bits [63:32].
477 */
478 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
479 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
480 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
481 MPIDR_AFFINITY_LEVEL(mpidr, 0));
482
483 typer = gic_read_typer(ptr + GICR_TYPER);
484 if ((typer >> 32) == aff) {
485 u64 offset = ptr - region->redist_base;
486 gic_data_rdist_rd_base() = ptr;
487 gic_data_rdist()->phys_base = region->phys_base + offset;
488
489 pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
490 smp_processor_id(), mpidr,
491 (int)(region - gic_data.redist_regions),
492 &gic_data_rdist()->phys_base);
493 return 0;
494 }
495
496 /* Try next one */
497 return 1;
498}
499
500static int gic_populate_rdist(void)
501{
502 if (gic_iterate_rdists(__gic_populate_rdist) == 0)
503 return 0;
504
Marc Zyngier021f6532014-06-30 16:01:31 +0100505 /* We couldn't even deal with ourselves... */
Jean-Philippe Bruckerf6c86a42015-10-01 13:47:15 +0100506 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
Marc Zyngier0d94ded2016-12-19 17:00:38 +0000507 smp_processor_id(),
508 (unsigned long)cpu_logical_map(smp_processor_id()));
Marc Zyngier021f6532014-06-30 16:01:31 +0100509 return -ENODEV;
510}
511
Marc Zyngier0edc23e2016-12-19 17:01:52 +0000512static int __gic_update_vlpi_properties(struct redist_region *region,
513 void __iomem *ptr)
514{
515 u64 typer = gic_read_typer(ptr + GICR_TYPER);
516 gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS);
517 gic_data.rdists.has_direct_lpi &= !!(typer & GICR_TYPER_DirectLPIS);
518
519 return 1;
520}
521
522static void gic_update_vlpi_properties(void)
523{
524 gic_iterate_rdists(__gic_update_vlpi_properties);
525 pr_info("%sVLPI support, %sdirect LPI support\n",
526 !gic_data.rdists.has_vlpis ? "no " : "",
527 !gic_data.rdists.has_direct_lpi ? "no " : "");
528}
529
Sudeep Holla3708d522014-08-26 16:03:35 +0100530static void gic_cpu_sys_reg_init(void)
Marc Zyngier021f6532014-06-30 16:01:31 +0100531{
Shanker Donthinenieda0d042017-10-06 10:24:00 -0500532 int i, cpu = smp_processor_id();
533 u64 mpidr = cpu_logical_map(cpu);
534 u64 need_rss = MPIDR_RS(mpidr);
Marc Zyngierd6062a62018-03-09 14:53:19 +0000535 u32 val;
Shanker Donthinenieda0d042017-10-06 10:24:00 -0500536
Marc Zyngier7cabd002015-09-30 11:48:01 +0100537 /*
538 * Need to check that the SRE bit has actually been set. If
539 * not, it means that SRE is disabled at EL2. We're going to
540 * die painfully, and there is nothing we can do about it.
541 *
542 * Kindly inform the luser.
543 */
544 if (!gic_enable_sre())
545 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
Marc Zyngier021f6532014-06-30 16:01:31 +0100546
547 /* Set priority mask register */
548 gic_write_pmr(DEFAULT_PMR_VALUE);
549
Daniel Thompson91ef8442016-08-19 17:13:09 +0100550 /*
551 * Some firmwares hand over to the kernel with the BPR changed from
552 * its reset value (and with a value large enough to prevent
553 * any pre-emptive interrupts from working at all). Writing a zero
554 * to BPR restores is reset value.
555 */
556 gic_write_bpr1(0);
557
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100558 if (static_key_true(&supports_deactivate)) {
559 /* EOI drops priority only (mode 1) */
560 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
561 } else {
562 /* EOI deactivates interrupt too (mode 0) */
563 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
564 }
Marc Zyngier021f6532014-06-30 16:01:31 +0100565
Marc Zyngierd6062a62018-03-09 14:53:19 +0000566 val = gic_read_ctlr();
567 val &= ICC_CTLR_EL1_PRI_BITS_MASK;
568 val >>= ICC_CTLR_EL1_PRI_BITS_SHIFT;
569
570 switch(val + 1) {
571 case 8:
572 case 7:
573 write_gicreg(0, ICC_AP0R3_EL1);
574 write_gicreg(0, ICC_AP1R3_EL1);
575 write_gicreg(0, ICC_AP0R2_EL1);
576 write_gicreg(0, ICC_AP1R2_EL1);
577 case 6:
578 write_gicreg(0, ICC_AP0R1_EL1);
579 write_gicreg(0, ICC_AP1R1_EL1);
580 case 5:
581 case 4:
582 write_gicreg(0, ICC_AP0R0_EL1);
583 write_gicreg(0, ICC_AP1R0_EL1);
584 }
585
586 isb();
587
Marc Zyngier021f6532014-06-30 16:01:31 +0100588 /* ... and let's hit the road... */
589 gic_write_grpen1(1);
Shanker Donthinenieda0d042017-10-06 10:24:00 -0500590
591 /* Keep the RSS capability status in per_cpu variable */
592 per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS);
593
594 /* Check all the CPUs have capable of sending SGIs to other CPUs */
595 for_each_online_cpu(i) {
596 bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu);
597
598 need_rss |= MPIDR_RS(cpu_logical_map(i));
599 if (need_rss && (!have_rss))
600 pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n",
601 cpu, (unsigned long)mpidr,
602 i, (unsigned long)cpu_logical_map(i));
603 }
604
605 /**
606 * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0,
607 * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED
608 * UNPREDICTABLE choice of :
609 * - The write is ignored.
610 * - The RS field is treated as 0.
611 */
612 if (need_rss && (!gic_data.has_rss))
613 pr_crit_once("RSS is required but GICD doesn't support it\n");
Marc Zyngier021f6532014-06-30 16:01:31 +0100614}
615
Marc Zyngierf736d652018-02-25 11:27:04 +0000616static bool gicv3_nolpi;
617
618static int __init gicv3_nolpi_cfg(char *buf)
619{
620 return strtobool(buf, &gicv3_nolpi);
621}
622early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg);
623
Marc Zyngierda33f312014-11-24 14:35:18 +0000624static int gic_dist_supports_lpis(void)
625{
Marc Zyngierf736d652018-02-25 11:27:04 +0000626 return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) && !gicv3_nolpi;
Marc Zyngierda33f312014-11-24 14:35:18 +0000627}
628
Marc Zyngier021f6532014-06-30 16:01:31 +0100629static void gic_cpu_init(void)
630{
631 void __iomem *rbase;
632
633 /* Register ourselves with the rest of the world */
634 if (gic_populate_rdist())
635 return;
636
Sudeep Hollaa2c22512014-08-26 16:03:34 +0100637 gic_enable_redist(true);
Marc Zyngier021f6532014-06-30 16:01:31 +0100638
639 rbase = gic_data_rdist_sgi_base();
640
Marc Zyngier7c9b9732016-05-06 19:41:56 +0100641 /* Configure SGIs/PPIs as non-secure Group-1 */
642 writel_relaxed(~0, rbase + GICR_IGROUPR0);
643
Marc Zyngier021f6532014-06-30 16:01:31 +0100644 gic_cpu_config(rbase, gic_redist_wait_for_rwp);
645
Marc Zyngierda33f312014-11-24 14:35:18 +0000646 /* Give LPIs a spin */
647 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
648 its_cpu_init();
649
Sudeep Holla3708d522014-08-26 16:03:35 +0100650 /* initialise system registers */
651 gic_cpu_sys_reg_init();
Marc Zyngier021f6532014-06-30 16:01:31 +0100652}
653
654#ifdef CONFIG_SMP
Marc Zyngier021f6532014-06-30 16:01:31 +0100655
Shanker Donthinenieda0d042017-10-06 10:24:00 -0500656#define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT)
657#define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL)
658
Richard Cochran6670a6d2016-07-13 17:16:05 +0000659static int gic_starting_cpu(unsigned int cpu)
660{
661 gic_cpu_init();
662 return 0;
663}
Marc Zyngier021f6532014-06-30 16:01:31 +0100664
665static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
Jean-Philippe Bruckerf6c86a42015-10-01 13:47:15 +0100666 unsigned long cluster_id)
Marc Zyngier021f6532014-06-30 16:01:31 +0100667{
James Morse727653d2016-09-19 18:29:15 +0100668 int next_cpu, cpu = *base_cpu;
Jean-Philippe Bruckerf6c86a42015-10-01 13:47:15 +0100669 unsigned long mpidr = cpu_logical_map(cpu);
Marc Zyngier021f6532014-06-30 16:01:31 +0100670 u16 tlist = 0;
671
672 while (cpu < nr_cpu_ids) {
Marc Zyngier021f6532014-06-30 16:01:31 +0100673 tlist |= 1 << (mpidr & 0xf);
674
James Morse727653d2016-09-19 18:29:15 +0100675 next_cpu = cpumask_next(cpu, mask);
676 if (next_cpu >= nr_cpu_ids)
Marc Zyngier021f6532014-06-30 16:01:31 +0100677 goto out;
James Morse727653d2016-09-19 18:29:15 +0100678 cpu = next_cpu;
Marc Zyngier021f6532014-06-30 16:01:31 +0100679
680 mpidr = cpu_logical_map(cpu);
681
Shanker Donthinenieda0d042017-10-06 10:24:00 -0500682 if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) {
Marc Zyngier021f6532014-06-30 16:01:31 +0100683 cpu--;
684 goto out;
685 }
686 }
687out:
688 *base_cpu = cpu;
689 return tlist;
690}
691
Andre Przywara7e580272014-11-12 13:46:06 +0000692#define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
693 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
694 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
695
Marc Zyngier021f6532014-06-30 16:01:31 +0100696static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
697{
698 u64 val;
699
Andre Przywara7e580272014-11-12 13:46:06 +0000700 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) |
701 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) |
702 irq << ICC_SGI1R_SGI_ID_SHIFT |
703 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) |
Shanker Donthinenieda0d042017-10-06 10:24:00 -0500704 MPIDR_TO_SGI_RS(cluster_id) |
Andre Przywara7e580272014-11-12 13:46:06 +0000705 tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
Marc Zyngier021f6532014-06-30 16:01:31 +0100706
Mark Salterb6dd4d82018-02-02 09:20:29 -0500707 pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
Marc Zyngier021f6532014-06-30 16:01:31 +0100708 gic_write_sgi1r(val);
709}
710
711static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
712{
713 int cpu;
714
715 if (WARN_ON(irq >= 16))
716 return;
717
718 /*
719 * Ensure that stores to Normal memory are visible to the
720 * other CPUs before issuing the IPI.
721 */
Shanker Donthineni21ec30c2018-01-31 18:03:42 -0600722 wmb();
Marc Zyngier021f6532014-06-30 16:01:31 +0100723
Rusty Russellf9b531f2015-03-05 10:49:16 +1030724 for_each_cpu(cpu, mask) {
Shanker Donthinenieda0d042017-10-06 10:24:00 -0500725 u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
Marc Zyngier021f6532014-06-30 16:01:31 +0100726 u16 tlist;
727
728 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
729 gic_send_sgi(cluster_id, tlist, irq);
730 }
731
732 /* Force the above writes to ICC_SGI1R_EL1 to be executed */
733 isb();
734}
735
736static void gic_smp_init(void)
737{
738 set_smp_cross_call(gic_raise_softirq);
Thomas Gleixner6896bcd2016-12-21 20:19:56 +0100739 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
Thomas Gleixner73c1b412016-12-21 20:19:54 +0100740 "irqchip/arm/gicv3:starting",
741 gic_starting_cpu, NULL);
Marc Zyngier021f6532014-06-30 16:01:31 +0100742}
743
744static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
745 bool force)
746{
Suzuki K Poulose65a30f82017-07-04 10:56:35 +0100747 unsigned int cpu;
Marc Zyngier021f6532014-06-30 16:01:31 +0100748 void __iomem *reg;
749 int enabled;
750 u64 val;
751
Suzuki K Poulose65a30f82017-07-04 10:56:35 +0100752 if (force)
753 cpu = cpumask_first(mask_val);
754 else
755 cpu = cpumask_any_and(mask_val, cpu_online_mask);
756
Suzuki K Poulose866d7c12017-06-30 10:58:28 +0100757 if (cpu >= nr_cpu_ids)
758 return -EINVAL;
759
Marc Zyngier021f6532014-06-30 16:01:31 +0100760 if (gic_irq_in_rdist(d))
761 return -EINVAL;
762
763 /* If interrupt was enabled, disable it first */
764 enabled = gic_peek_irq(d, GICD_ISENABLER);
765 if (enabled)
766 gic_mask_irq(d);
767
768 reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
769 val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
770
Jean-Philippe Brucker72c97122015-10-01 13:47:16 +0100771 gic_write_irouter(val, reg);
Marc Zyngier021f6532014-06-30 16:01:31 +0100772
773 /*
774 * If the interrupt was enabled, enabled it again. Otherwise,
775 * just wait for the distributor to have digested our changes.
776 */
777 if (enabled)
778 gic_unmask_irq(d);
779 else
780 gic_dist_wait_for_rwp();
781
Marc Zyngier956ae912017-08-18 09:39:17 +0100782 irq_data_update_effective_affinity(d, cpumask_of(cpu));
783
Antoine Tenart0fc6fa22016-02-19 16:22:43 +0100784 return IRQ_SET_MASK_OK_DONE;
Marc Zyngier021f6532014-06-30 16:01:31 +0100785}
786#else
787#define gic_set_affinity NULL
788#define gic_smp_init() do { } while(0)
789#endif
790
Sudeep Holla3708d522014-08-26 16:03:35 +0100791#ifdef CONFIG_CPU_PM
Sudeep Hollaccd94322016-08-17 13:49:19 +0100792/* Check whether it's single security state view */
793static bool gic_dist_security_disabled(void)
794{
795 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS;
796}
797
Sudeep Holla3708d522014-08-26 16:03:35 +0100798static int gic_cpu_pm_notifier(struct notifier_block *self,
799 unsigned long cmd, void *v)
800{
801 if (cmd == CPU_PM_EXIT) {
Sudeep Hollaccd94322016-08-17 13:49:19 +0100802 if (gic_dist_security_disabled())
803 gic_enable_redist(true);
Sudeep Holla3708d522014-08-26 16:03:35 +0100804 gic_cpu_sys_reg_init();
Sudeep Hollaccd94322016-08-17 13:49:19 +0100805 } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) {
Sudeep Holla3708d522014-08-26 16:03:35 +0100806 gic_write_grpen1(0);
807 gic_enable_redist(false);
808 }
809 return NOTIFY_OK;
810}
811
812static struct notifier_block gic_cpu_pm_notifier_block = {
813 .notifier_call = gic_cpu_pm_notifier,
814};
815
816static void gic_cpu_pm_init(void)
817{
818 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
819}
820
821#else
822static inline void gic_cpu_pm_init(void) { }
823#endif /* CONFIG_CPU_PM */
824
Marc Zyngier021f6532014-06-30 16:01:31 +0100825static struct irq_chip gic_chip = {
826 .name = "GICv3",
827 .irq_mask = gic_mask_irq,
828 .irq_unmask = gic_unmask_irq,
829 .irq_eoi = gic_eoi_irq,
830 .irq_set_type = gic_set_type,
831 .irq_set_affinity = gic_set_affinity,
Marc Zyngierb594c6e2015-03-18 11:01:24 +0000832 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
833 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
Sudeep Holla55963c92015-06-05 11:59:57 +0100834 .flags = IRQCHIP_SET_TYPE_MASKED,
Marc Zyngier021f6532014-06-30 16:01:31 +0100835};
836
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100837static struct irq_chip gic_eoimode1_chip = {
838 .name = "GICv3",
839 .irq_mask = gic_eoimode1_mask_irq,
840 .irq_unmask = gic_unmask_irq,
841 .irq_eoi = gic_eoimode1_eoi_irq,
842 .irq_set_type = gic_set_type,
843 .irq_set_affinity = gic_set_affinity,
844 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
845 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
Marc Zyngier530bf352015-08-26 17:00:43 +0100846 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100847 .flags = IRQCHIP_SET_TYPE_MASKED,
848};
849
Marc Zyngierda33f312014-11-24 14:35:18 +0000850#define GIC_ID_NR (1U << gic_data.rdists.id_bits)
851
Marc Zyngier021f6532014-06-30 16:01:31 +0100852static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
853 irq_hw_number_t hw)
854{
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100855 struct irq_chip *chip = &gic_chip;
856
857 if (static_key_true(&supports_deactivate))
858 chip = &gic_eoimode1_chip;
859
Marc Zyngier021f6532014-06-30 16:01:31 +0100860 /* SGIs are private to the core kernel */
861 if (hw < 16)
862 return -EPERM;
Marc Zyngierda33f312014-11-24 14:35:18 +0000863 /* Nothing here */
864 if (hw >= gic_data.irq_nr && hw < 8192)
865 return -EPERM;
866 /* Off limits */
867 if (hw >= GIC_ID_NR)
868 return -EPERM;
869
Marc Zyngier021f6532014-06-30 16:01:31 +0100870 /* PPIs */
871 if (hw < 32) {
872 irq_set_percpu_devid(irq);
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100873 irq_domain_set_info(d, irq, hw, chip, d->host_data,
Marc Zyngier443acc42014-11-24 14:35:09 +0000874 handle_percpu_devid_irq, NULL, NULL);
Rob Herringd17cab42015-08-29 18:01:22 -0500875 irq_set_status_flags(irq, IRQ_NOAUTOEN);
Marc Zyngier021f6532014-06-30 16:01:31 +0100876 }
877 /* SPIs */
878 if (hw >= 32 && hw < gic_data.irq_nr) {
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100879 irq_domain_set_info(d, irq, hw, chip, d->host_data,
Marc Zyngier443acc42014-11-24 14:35:09 +0000880 handle_fasteoi_irq, NULL, NULL);
Rob Herringd17cab42015-08-29 18:01:22 -0500881 irq_set_probe(irq);
Marc Zyngier956ae912017-08-18 09:39:17 +0100882 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
Marc Zyngier021f6532014-06-30 16:01:31 +0100883 }
Marc Zyngierda33f312014-11-24 14:35:18 +0000884 /* LPIs */
885 if (hw >= 8192 && hw < GIC_ID_NR) {
886 if (!gic_dist_supports_lpis())
887 return -EPERM;
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100888 irq_domain_set_info(d, irq, hw, chip, d->host_data,
Marc Zyngierda33f312014-11-24 14:35:18 +0000889 handle_fasteoi_irq, NULL, NULL);
Marc Zyngierda33f312014-11-24 14:35:18 +0000890 }
891
Marc Zyngier021f6532014-06-30 16:01:31 +0100892 return 0;
893}
894
Marc Zyngierf833f572015-10-13 12:51:33 +0100895static int gic_irq_domain_translate(struct irq_domain *d,
896 struct irq_fwspec *fwspec,
897 unsigned long *hwirq,
898 unsigned int *type)
Marc Zyngier021f6532014-06-30 16:01:31 +0100899{
Marc Zyngierf833f572015-10-13 12:51:33 +0100900 if (is_of_node(fwspec->fwnode)) {
901 if (fwspec->param_count < 3)
902 return -EINVAL;
Marc Zyngier021f6532014-06-30 16:01:31 +0100903
Marc Zyngierdb8c70e2015-10-14 12:27:16 +0100904 switch (fwspec->param[0]) {
905 case 0: /* SPI */
906 *hwirq = fwspec->param[1] + 32;
907 break;
908 case 1: /* PPI */
909 *hwirq = fwspec->param[1] + 16;
910 break;
911 case GIC_IRQ_TYPE_LPI: /* LPI */
912 *hwirq = fwspec->param[1];
913 break;
914 default:
915 return -EINVAL;
916 }
Marc Zyngierf833f572015-10-13 12:51:33 +0100917
918 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
919 return 0;
Marc Zyngier021f6532014-06-30 16:01:31 +0100920 }
921
Tomasz Nowickiffa7d612016-01-19 14:11:15 +0100922 if (is_fwnode_irqchip(fwspec->fwnode)) {
923 if(fwspec->param_count != 2)
924 return -EINVAL;
925
926 *hwirq = fwspec->param[0];
927 *type = fwspec->param[1];
928 return 0;
929 }
930
Marc Zyngierf833f572015-10-13 12:51:33 +0100931 return -EINVAL;
Marc Zyngier021f6532014-06-30 16:01:31 +0100932}
933
Marc Zyngier443acc42014-11-24 14:35:09 +0000934static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
935 unsigned int nr_irqs, void *arg)
936{
937 int i, ret;
938 irq_hw_number_t hwirq;
939 unsigned int type = IRQ_TYPE_NONE;
Marc Zyngierf833f572015-10-13 12:51:33 +0100940 struct irq_fwspec *fwspec = arg;
Marc Zyngier443acc42014-11-24 14:35:09 +0000941
Marc Zyngierf833f572015-10-13 12:51:33 +0100942 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
Marc Zyngier443acc42014-11-24 14:35:09 +0000943 if (ret)
944 return ret;
945
Suzuki K Poulose63c16c62017-07-04 10:56:33 +0100946 for (i = 0; i < nr_irqs; i++) {
947 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
948 if (ret)
949 return ret;
950 }
Marc Zyngier443acc42014-11-24 14:35:09 +0000951
952 return 0;
953}
954
955static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
956 unsigned int nr_irqs)
957{
958 int i;
959
960 for (i = 0; i < nr_irqs; i++) {
961 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
962 irq_set_handler(virq + i, NULL);
963 irq_domain_reset_irq_data(d);
964 }
965}
966
Marc Zyngiere3825ba2016-04-11 09:57:54 +0100967static int gic_irq_domain_select(struct irq_domain *d,
968 struct irq_fwspec *fwspec,
969 enum irq_domain_bus_token bus_token)
970{
971 /* Not for us */
972 if (fwspec->fwnode != d->fwnode)
973 return 0;
974
975 /* If this is not DT, then we have a single domain */
976 if (!is_of_node(fwspec->fwnode))
977 return 1;
978
979 /*
980 * If this is a PPI and we have a 4th (non-null) parameter,
981 * then we need to match the partition domain.
982 */
983 if (fwspec->param_count >= 4 &&
984 fwspec->param[0] == 1 && fwspec->param[3] != 0)
985 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]);
986
987 return d == gic_data.domain;
988}
989
Marc Zyngier021f6532014-06-30 16:01:31 +0100990static const struct irq_domain_ops gic_irq_domain_ops = {
Marc Zyngierf833f572015-10-13 12:51:33 +0100991 .translate = gic_irq_domain_translate,
Marc Zyngier443acc42014-11-24 14:35:09 +0000992 .alloc = gic_irq_domain_alloc,
993 .free = gic_irq_domain_free,
Marc Zyngiere3825ba2016-04-11 09:57:54 +0100994 .select = gic_irq_domain_select,
995};
996
997static int partition_domain_translate(struct irq_domain *d,
998 struct irq_fwspec *fwspec,
999 unsigned long *hwirq,
1000 unsigned int *type)
1001{
1002 struct device_node *np;
1003 int ret;
1004
1005 np = of_find_node_by_phandle(fwspec->param[3]);
1006 if (WARN_ON(!np))
1007 return -EINVAL;
1008
1009 ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]],
1010 of_node_to_fwnode(np));
1011 if (ret < 0)
1012 return ret;
1013
1014 *hwirq = ret;
1015 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1016
1017 return 0;
1018}
1019
1020static const struct irq_domain_ops partition_domain_ops = {
1021 .translate = partition_domain_translate,
1022 .select = gic_irq_domain_select,
Marc Zyngier021f6532014-06-30 16:01:31 +01001023};
1024
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001025static int __init gic_init_bases(void __iomem *dist_base,
1026 struct redist_region *rdist_regs,
1027 u32 nr_redist_regions,
1028 u64 redist_stride,
1029 struct fwnode_handle *handle)
1030{
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001031 u32 typer;
1032 int gic_irqs;
1033 int err;
1034
1035 if (!is_hyp_mode_available())
1036 static_key_slow_dec(&supports_deactivate);
1037
1038 if (static_key_true(&supports_deactivate))
1039 pr_info("GIC: Using split EOI/Deactivate mode\n");
1040
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001041 gic_data.fwnode = handle;
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001042 gic_data.dist_base = dist_base;
1043 gic_data.redist_regions = rdist_regs;
1044 gic_data.nr_redist_regions = nr_redist_regions;
1045 gic_data.redist_stride = redist_stride;
1046
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001047 /*
1048 * Find out how many interrupts are supported.
1049 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
1050 */
1051 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
1052 gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer);
1053 gic_irqs = GICD_TYPER_IRQS(typer);
1054 if (gic_irqs > 1020)
1055 gic_irqs = 1020;
1056 gic_data.irq_nr = gic_irqs;
1057
1058 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
1059 &gic_data);
1060 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
Marc Zyngier0edc23e2016-12-19 17:01:52 +00001061 gic_data.rdists.has_vlpis = true;
1062 gic_data.rdists.has_direct_lpi = true;
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001063
1064 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
1065 err = -ENOMEM;
1066 goto out_free;
1067 }
1068
Shanker Donthinenieda0d042017-10-06 10:24:00 -05001069 gic_data.has_rss = !!(typer & GICD_TYPER_RSS);
1070 pr_info("Distributor has %sRange Selector support\n",
1071 gic_data.has_rss ? "" : "no ");
1072
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001073 set_handle_irq(gic_handle_irq);
1074
Marc Zyngier0edc23e2016-12-19 17:01:52 +00001075 gic_update_vlpi_properties();
1076
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02001077 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
1078 its_init(handle, &gic_data.rdists, gic_data.domain);
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001079
1080 gic_smp_init();
1081 gic_dist_init();
1082 gic_cpu_init();
1083 gic_cpu_pm_init();
1084
1085 return 0;
1086
1087out_free:
1088 if (gic_data.domain)
1089 irq_domain_remove(gic_data.domain);
1090 free_percpu(gic_data.rdists.rdist);
1091 return err;
1092}
1093
1094static int __init gic_validate_dist_version(void __iomem *dist_base)
1095{
1096 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
1097
1098 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
1099 return -ENODEV;
1100
1101 return 0;
1102}
1103
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001104/* Create all possible partitions at boot time */
Linus Torvalds7beaa242016-05-19 11:27:09 -07001105static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001106{
1107 struct device_node *parts_node, *child_part;
1108 int part_idx = 0, i;
1109 int nr_parts;
1110 struct partition_affinity *parts;
1111
Johan Hovold00ee9a12017-11-11 17:51:25 +01001112 parts_node = of_get_child_by_name(gic_node, "ppi-partitions");
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001113 if (!parts_node)
1114 return;
1115
1116 nr_parts = of_get_child_count(parts_node);
1117
1118 if (!nr_parts)
Johan Hovold00ee9a12017-11-11 17:51:25 +01001119 goto out_put_node;
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001120
1121 parts = kzalloc(sizeof(*parts) * nr_parts, GFP_KERNEL);
1122 if (WARN_ON(!parts))
Johan Hovold00ee9a12017-11-11 17:51:25 +01001123 goto out_put_node;
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001124
1125 for_each_child_of_node(parts_node, child_part) {
1126 struct partition_affinity *part;
1127 int n;
1128
1129 part = &parts[part_idx];
1130
1131 part->partition_id = of_node_to_fwnode(child_part);
1132
1133 pr_info("GIC: PPI partition %s[%d] { ",
1134 child_part->name, part_idx);
1135
1136 n = of_property_count_elems_of_size(child_part, "affinity",
1137 sizeof(u32));
1138 WARN_ON(n <= 0);
1139
1140 for (i = 0; i < n; i++) {
1141 int err, cpu;
1142 u32 cpu_phandle;
1143 struct device_node *cpu_node;
1144
1145 err = of_property_read_u32_index(child_part, "affinity",
1146 i, &cpu_phandle);
1147 if (WARN_ON(err))
1148 continue;
1149
1150 cpu_node = of_find_node_by_phandle(cpu_phandle);
1151 if (WARN_ON(!cpu_node))
1152 continue;
1153
Suzuki K Poulosec08ec7d2018-01-02 11:25:29 +00001154 cpu = of_cpu_node_to_id(cpu_node);
1155 if (WARN_ON(cpu < 0))
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001156 continue;
1157
Rob Herringe81f54c2017-07-18 16:43:10 -05001158 pr_cont("%pOF[%d] ", cpu_node, cpu);
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001159
1160 cpumask_set_cpu(cpu, &part->mask);
1161 }
1162
1163 pr_cont("}\n");
1164 part_idx++;
1165 }
1166
1167 for (i = 0; i < 16; i++) {
1168 unsigned int irq;
1169 struct partition_desc *desc;
1170 struct irq_fwspec ppi_fwspec = {
1171 .fwnode = gic_data.fwnode,
1172 .param_count = 3,
1173 .param = {
1174 [0] = 1,
1175 [1] = i,
1176 [2] = IRQ_TYPE_NONE,
1177 },
1178 };
1179
1180 irq = irq_create_fwspec_mapping(&ppi_fwspec);
1181 if (WARN_ON(!irq))
1182 continue;
1183 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts,
1184 irq, &partition_domain_ops);
1185 if (WARN_ON(!desc))
1186 continue;
1187
1188 gic_data.ppi_descs[i] = desc;
1189 }
Johan Hovold00ee9a12017-11-11 17:51:25 +01001190
1191out_put_node:
1192 of_node_put(parts_node);
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001193}
1194
Julien Grall1839e572016-04-11 16:32:57 +01001195static void __init gic_of_setup_kvm_info(struct device_node *node)
1196{
1197 int ret;
1198 struct resource r;
1199 u32 gicv_idx;
1200
1201 gic_v3_kvm_info.type = GIC_V3;
1202
1203 gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1204 if (!gic_v3_kvm_info.maint_irq)
1205 return;
1206
1207 if (of_property_read_u32(node, "#redistributor-regions",
1208 &gicv_idx))
1209 gicv_idx = 1;
1210
1211 gicv_idx += 3; /* Also skip GICD, GICC, GICH */
1212 ret = of_address_to_resource(node, gicv_idx, &r);
1213 if (!ret)
1214 gic_v3_kvm_info.vcpu = r;
1215
Marc Zyngier4bdf5022017-06-25 14:10:46 +01001216 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
Julien Grall1839e572016-04-11 16:32:57 +01001217 gic_set_kvm_info(&gic_v3_kvm_info);
1218}
1219
Marc Zyngier021f6532014-06-30 16:01:31 +01001220static int __init gic_of_init(struct device_node *node, struct device_node *parent)
1221{
1222 void __iomem *dist_base;
Marc Zyngierf5c14342014-11-24 14:35:10 +00001223 struct redist_region *rdist_regs;
Marc Zyngier021f6532014-06-30 16:01:31 +01001224 u64 redist_stride;
Marc Zyngierf5c14342014-11-24 14:35:10 +00001225 u32 nr_redist_regions;
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001226 int err, i;
Marc Zyngier021f6532014-06-30 16:01:31 +01001227
1228 dist_base = of_iomap(node, 0);
1229 if (!dist_base) {
Rob Herringe81f54c2017-07-18 16:43:10 -05001230 pr_err("%pOF: unable to map gic dist registers\n", node);
Marc Zyngier021f6532014-06-30 16:01:31 +01001231 return -ENXIO;
1232 }
1233
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001234 err = gic_validate_dist_version(dist_base);
1235 if (err) {
Rob Herringe81f54c2017-07-18 16:43:10 -05001236 pr_err("%pOF: no distributor detected, giving up\n", node);
Marc Zyngier021f6532014-06-30 16:01:31 +01001237 goto out_unmap_dist;
1238 }
1239
Marc Zyngierf5c14342014-11-24 14:35:10 +00001240 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
1241 nr_redist_regions = 1;
Marc Zyngier021f6532014-06-30 16:01:31 +01001242
Marc Zyngierf5c14342014-11-24 14:35:10 +00001243 rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL);
1244 if (!rdist_regs) {
Marc Zyngier021f6532014-06-30 16:01:31 +01001245 err = -ENOMEM;
1246 goto out_unmap_dist;
1247 }
1248
Marc Zyngierf5c14342014-11-24 14:35:10 +00001249 for (i = 0; i < nr_redist_regions; i++) {
1250 struct resource res;
1251 int ret;
1252
1253 ret = of_address_to_resource(node, 1 + i, &res);
1254 rdist_regs[i].redist_base = of_iomap(node, 1 + i);
1255 if (ret || !rdist_regs[i].redist_base) {
Rob Herringe81f54c2017-07-18 16:43:10 -05001256 pr_err("%pOF: couldn't map region %d\n", node, i);
Marc Zyngier021f6532014-06-30 16:01:31 +01001257 err = -ENODEV;
1258 goto out_unmap_rdist;
1259 }
Marc Zyngierf5c14342014-11-24 14:35:10 +00001260 rdist_regs[i].phys_base = res.start;
Marc Zyngier021f6532014-06-30 16:01:31 +01001261 }
1262
1263 if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
1264 redist_stride = 0;
1265
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001266 err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
1267 redist_stride, &node->fwnode);
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001268 if (err)
1269 goto out_unmap_rdist;
1270
1271 gic_populate_ppi_partitions(node);
Christoffer Dalld33a3c82016-12-06 22:00:52 +01001272
1273 if (static_key_true(&supports_deactivate))
1274 gic_of_setup_kvm_info(node);
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001275 return 0;
Marc Zyngier0b6a3da2015-08-26 17:00:42 +01001276
Marc Zyngier021f6532014-06-30 16:01:31 +01001277out_unmap_rdist:
Marc Zyngierf5c14342014-11-24 14:35:10 +00001278 for (i = 0; i < nr_redist_regions; i++)
1279 if (rdist_regs[i].redist_base)
1280 iounmap(rdist_regs[i].redist_base);
1281 kfree(rdist_regs);
Marc Zyngier021f6532014-06-30 16:01:31 +01001282out_unmap_dist:
1283 iounmap(dist_base);
1284 return err;
1285}
1286
1287IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001288
1289#ifdef CONFIG_ACPI
Julien Grall611f0392016-04-11 16:32:56 +01001290static struct
1291{
1292 void __iomem *dist_base;
1293 struct redist_region *redist_regs;
1294 u32 nr_redist_regions;
1295 bool single_redist;
Julien Grall1839e572016-04-11 16:32:57 +01001296 u32 maint_irq;
1297 int maint_irq_mode;
1298 phys_addr_t vcpu_base;
Julien Grall611f0392016-04-11 16:32:56 +01001299} acpi_data __initdata;
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001300
1301static void __init
1302gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base)
1303{
1304 static int count = 0;
1305
Julien Grall611f0392016-04-11 16:32:56 +01001306 acpi_data.redist_regs[count].phys_base = phys_base;
1307 acpi_data.redist_regs[count].redist_base = redist_base;
1308 acpi_data.redist_regs[count].single_redist = acpi_data.single_redist;
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001309 count++;
1310}
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001311
1312static int __init
1313gic_acpi_parse_madt_redist(struct acpi_subtable_header *header,
1314 const unsigned long end)
1315{
1316 struct acpi_madt_generic_redistributor *redist =
1317 (struct acpi_madt_generic_redistributor *)header;
1318 void __iomem *redist_base;
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001319
1320 redist_base = ioremap(redist->base_address, redist->length);
1321 if (!redist_base) {
1322 pr_err("Couldn't map GICR region @%llx\n", redist->base_address);
1323 return -ENOMEM;
1324 }
1325
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001326 gic_acpi_register_redist(redist->base_address, redist_base);
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001327 return 0;
1328}
1329
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001330static int __init
1331gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header,
1332 const unsigned long end)
1333{
1334 struct acpi_madt_generic_interrupt *gicc =
1335 (struct acpi_madt_generic_interrupt *)header;
Julien Grall611f0392016-04-11 16:32:56 +01001336 u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001337 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
1338 void __iomem *redist_base;
1339
Shanker Donthineniebe2f872017-12-05 13:16:21 -06001340 /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */
1341 if (!(gicc->flags & ACPI_MADT_ENABLED))
1342 return 0;
1343
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001344 redist_base = ioremap(gicc->gicr_base_address, size);
1345 if (!redist_base)
1346 return -ENOMEM;
1347
1348 gic_acpi_register_redist(gicc->gicr_base_address, redist_base);
1349 return 0;
1350}
1351
1352static int __init gic_acpi_collect_gicr_base(void)
1353{
1354 acpi_tbl_entry_handler redist_parser;
1355 enum acpi_madt_type type;
1356
Julien Grall611f0392016-04-11 16:32:56 +01001357 if (acpi_data.single_redist) {
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001358 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT;
1359 redist_parser = gic_acpi_parse_madt_gicc;
1360 } else {
1361 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR;
1362 redist_parser = gic_acpi_parse_madt_redist;
1363 }
1364
1365 /* Collect redistributor base addresses in GICR entries */
1366 if (acpi_table_parse_madt(type, redist_parser, 0) > 0)
1367 return 0;
1368
1369 pr_info("No valid GICR entries exist\n");
1370 return -ENODEV;
1371}
1372
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001373static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header,
1374 const unsigned long end)
1375{
1376 /* Subtable presence means that redist exists, that's it */
1377 return 0;
1378}
1379
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001380static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header,
1381 const unsigned long end)
1382{
1383 struct acpi_madt_generic_interrupt *gicc =
1384 (struct acpi_madt_generic_interrupt *)header;
1385
1386 /*
1387 * If GICC is enabled and has valid gicr base address, then it means
1388 * GICR base is presented via GICC
1389 */
1390 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address)
1391 return 0;
1392
Shanker Donthineniebe2f872017-12-05 13:16:21 -06001393 /*
1394 * It's perfectly valid firmware can pass disabled GICC entry, driver
1395 * should not treat as errors, skip the entry instead of probe fail.
1396 */
1397 if (!(gicc->flags & ACPI_MADT_ENABLED))
1398 return 0;
1399
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001400 return -ENODEV;
1401}
1402
1403static int __init gic_acpi_count_gicr_regions(void)
1404{
1405 int count;
1406
1407 /*
1408 * Count how many redistributor regions we have. It is not allowed
1409 * to mix redistributor description, GICR and GICC subtables have to be
1410 * mutually exclusive.
1411 */
1412 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1413 gic_acpi_match_gicr, 0);
1414 if (count > 0) {
Julien Grall611f0392016-04-11 16:32:56 +01001415 acpi_data.single_redist = false;
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001416 return count;
1417 }
1418
1419 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1420 gic_acpi_match_gicc, 0);
1421 if (count > 0)
Julien Grall611f0392016-04-11 16:32:56 +01001422 acpi_data.single_redist = true;
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001423
1424 return count;
1425}
1426
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001427static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header,
1428 struct acpi_probe_entry *ape)
1429{
1430 struct acpi_madt_generic_distributor *dist;
1431 int count;
1432
1433 dist = (struct acpi_madt_generic_distributor *)header;
1434 if (dist->version != ape->driver_data)
1435 return false;
1436
1437 /* We need to do that exercise anyway, the sooner the better */
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001438 count = gic_acpi_count_gicr_regions();
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001439 if (count <= 0)
1440 return false;
1441
Julien Grall611f0392016-04-11 16:32:56 +01001442 acpi_data.nr_redist_regions = count;
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001443 return true;
1444}
1445
Julien Grall1839e572016-04-11 16:32:57 +01001446static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header,
1447 const unsigned long end)
1448{
1449 struct acpi_madt_generic_interrupt *gicc =
1450 (struct acpi_madt_generic_interrupt *)header;
1451 int maint_irq_mode;
1452 static int first_madt = true;
1453
1454 /* Skip unusable CPUs */
1455 if (!(gicc->flags & ACPI_MADT_ENABLED))
1456 return 0;
1457
1458 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
1459 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
1460
1461 if (first_madt) {
1462 first_madt = false;
1463
1464 acpi_data.maint_irq = gicc->vgic_interrupt;
1465 acpi_data.maint_irq_mode = maint_irq_mode;
1466 acpi_data.vcpu_base = gicc->gicv_base_address;
1467
1468 return 0;
1469 }
1470
1471 /*
1472 * The maintenance interrupt and GICV should be the same for every CPU
1473 */
1474 if ((acpi_data.maint_irq != gicc->vgic_interrupt) ||
1475 (acpi_data.maint_irq_mode != maint_irq_mode) ||
1476 (acpi_data.vcpu_base != gicc->gicv_base_address))
1477 return -EINVAL;
1478
1479 return 0;
1480}
1481
1482static bool __init gic_acpi_collect_virt_info(void)
1483{
1484 int count;
1485
1486 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1487 gic_acpi_parse_virt_madt_gicc, 0);
1488
1489 return (count > 0);
1490}
1491
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001492#define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
Julien Grall1839e572016-04-11 16:32:57 +01001493#define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
1494#define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
1495
1496static void __init gic_acpi_setup_kvm_info(void)
1497{
1498 int irq;
1499
1500 if (!gic_acpi_collect_virt_info()) {
1501 pr_warn("Unable to get hardware information used for virtualization\n");
1502 return;
1503 }
1504
1505 gic_v3_kvm_info.type = GIC_V3;
1506
1507 irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
1508 acpi_data.maint_irq_mode,
1509 ACPI_ACTIVE_HIGH);
1510 if (irq <= 0)
1511 return;
1512
1513 gic_v3_kvm_info.maint_irq = irq;
1514
1515 if (acpi_data.vcpu_base) {
1516 struct resource *vcpu = &gic_v3_kvm_info.vcpu;
1517
1518 vcpu->flags = IORESOURCE_MEM;
1519 vcpu->start = acpi_data.vcpu_base;
1520 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
1521 }
1522
Marc Zyngier4bdf5022017-06-25 14:10:46 +01001523 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
Julien Grall1839e572016-04-11 16:32:57 +01001524 gic_set_kvm_info(&gic_v3_kvm_info);
1525}
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001526
1527static int __init
1528gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end)
1529{
1530 struct acpi_madt_generic_distributor *dist;
1531 struct fwnode_handle *domain_handle;
Julien Grall611f0392016-04-11 16:32:56 +01001532 size_t size;
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001533 int i, err;
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001534
1535 /* Get distributor base address */
1536 dist = (struct acpi_madt_generic_distributor *)header;
Julien Grall611f0392016-04-11 16:32:56 +01001537 acpi_data.dist_base = ioremap(dist->base_address,
1538 ACPI_GICV3_DIST_MEM_SIZE);
1539 if (!acpi_data.dist_base) {
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001540 pr_err("Unable to map GICD registers\n");
1541 return -ENOMEM;
1542 }
1543
Julien Grall611f0392016-04-11 16:32:56 +01001544 err = gic_validate_dist_version(acpi_data.dist_base);
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001545 if (err) {
Arvind Yadav71192a682017-11-13 19:23:49 +05301546 pr_err("No distributor detected at @%p, giving up\n",
Julien Grall611f0392016-04-11 16:32:56 +01001547 acpi_data.dist_base);
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001548 goto out_dist_unmap;
1549 }
1550
Julien Grall611f0392016-04-11 16:32:56 +01001551 size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions;
1552 acpi_data.redist_regs = kzalloc(size, GFP_KERNEL);
1553 if (!acpi_data.redist_regs) {
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001554 err = -ENOMEM;
1555 goto out_dist_unmap;
1556 }
1557
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001558 err = gic_acpi_collect_gicr_base();
1559 if (err)
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001560 goto out_redist_unmap;
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001561
Julien Grall611f0392016-04-11 16:32:56 +01001562 domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base);
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001563 if (!domain_handle) {
1564 err = -ENOMEM;
1565 goto out_redist_unmap;
1566 }
1567
Julien Grall611f0392016-04-11 16:32:56 +01001568 err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs,
1569 acpi_data.nr_redist_regions, 0, domain_handle);
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001570 if (err)
1571 goto out_fwhandle_free;
1572
1573 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
Christoffer Dalld33a3c82016-12-06 22:00:52 +01001574
1575 if (static_key_true(&supports_deactivate))
1576 gic_acpi_setup_kvm_info();
Julien Grall1839e572016-04-11 16:32:57 +01001577
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001578 return 0;
1579
1580out_fwhandle_free:
1581 irq_domain_free_fwnode(domain_handle);
1582out_redist_unmap:
Julien Grall611f0392016-04-11 16:32:56 +01001583 for (i = 0; i < acpi_data.nr_redist_regions; i++)
1584 if (acpi_data.redist_regs[i].redist_base)
1585 iounmap(acpi_data.redist_regs[i].redist_base);
1586 kfree(acpi_data.redist_regs);
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001587out_dist_unmap:
Julien Grall611f0392016-04-11 16:32:56 +01001588 iounmap(acpi_data.dist_base);
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001589 return err;
1590}
1591IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1592 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3,
1593 gic_acpi_init);
1594IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1595 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4,
1596 gic_acpi_init);
1597IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1598 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE,
1599 gic_acpi_init);
1600#endif