blob: 601cf33040e28cffd0fe8b7fa6485bba55191b85 [file] [log] [blame]
Xiaohu.Huang83a0b702021-12-28 11:06:24 +08001/*
yang.li5bef2f62022-01-11 14:08:06 +08002 * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved.
Xiaohu.Huang83a0b702021-12-28 11:06:24 +08003 *
yang.li5bef2f62022-01-11 14:08:06 +08004 * SPDX-License-Identifier: MIT
Xiaohu.Huang83a0b702021-12-28 11:06:24 +08005 */
6
Xiaohu.Huang83a0b702021-12-28 11:06:24 +08007#ifndef __COMMON_H
8#define __COMMON_H
9
10#ifdef __cplusplus
11extern "C" {
12#endif
13#include <stdint.h>
14#include <errno.h>
15
Xiaohu.Huang83a0b702021-12-28 11:06:24 +080016/* Macros to access registers */
17#define REG32_ADDR(addr) ((volatile uint32_t *)(uintptr_t)(addr))
18#define REG16_ADDR(addr) ((volatile uint16_t *)(uintptr_t)(addr))
xiaohu.huange7678d12022-05-10 00:56:48 +080019#define REG8_ADDR(addr) ((volatile uint8_t *)(uintptr_t)(addr))
Xiaohu.Huang83a0b702021-12-28 11:06:24 +080020
21#define REG32(addr) (*REG32_ADDR(addr))
22#define REG16(addr) (*REG16_ADDR(addr))
xiaohu.huange7678d12022-05-10 00:56:48 +080023#define REG8(addr) (*REG8_ADDR(addr))
Xiaohu.Huang83a0b702021-12-28 11:06:24 +080024
xiaohu.huange7678d12022-05-10 00:56:48 +080025#define BIT(nr) (1UL << (nr))
26#define REG32_UPDATE_BITS(addr, mask, val) \
27 do { \
28 uint32_t _v = REG32((unsigned long)addr); \
29 _v &= (~(mask)); \
30 _v |= ((val) & (mask)); \
31 REG32((unsigned long)addr) = _v; \
32 } while (0)
Xiaohu.Huang83a0b702021-12-28 11:06:24 +080033
xiaohu.huang0a909552022-09-19 14:43:08 +080034static inline int generic_ffs(int x)
35{
36 int r = 1;
37
38 if (!x)
39 return 0;
40 if (!(x & 0xffff)) {
41 x >>= 16;
42 r += 16;
43 }
44 if (!(x & 0xff)) {
45 x >>= 8;
46 r += 8;
47 }
48 if (!(x & 0xf)) {
49 x >>= 4;
50 r += 4;
51 }
52 if (!(x & 3)) {
53 x >>= 2;
54 r += 2;
55 }
56 if (!(x & 1)) {
57 x >>= 1;
58 r += 1;
59 }
60 return r;
61}
62#define ffs(x) generic_ffs(x)
63
Xiaohu.Huang83a0b702021-12-28 11:06:24 +080064#ifndef FIELD_PREP
xiaohu.huange7678d12022-05-10 00:56:48 +080065#define FIELD_PREP(_mask, _val) (((typeof(_mask))(_val) << (ffs(_mask) - 1)) & (_mask))
Xiaohu.Huang83a0b702021-12-28 11:06:24 +080066#endif
67
68#ifndef FIELD_GET
xiaohu.huange7678d12022-05-10 00:56:48 +080069#define FIELD_GET(_mask, _reg) ((typeof(_mask))(((_reg) & (_mask)) >> (ffs(_mask) - 1)))
Xiaohu.Huang83a0b702021-12-28 11:06:24 +080070#endif
71
72#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
73
74#define BITS_PER_LONG (sizeof(unsigned long) == 8 ? 64 : 32)
xiaohu.huange7678d12022-05-10 00:56:48 +080075#define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
76#define IS_ALIGNED(x, a) (((unsigned long)(x) & ((unsigned long)(a)-1)) == 0)
77#define _RET_IP_ ((unsigned long)__builtin_return_address(0))
78#define _THIS_IP_ \
79 ({ \
80 __label__ __here; \
81__here: \
82 (unsigned long)&&__here; \
83 })
Xiaohu.Huang83a0b702021-12-28 11:06:24 +080084#define __round_mask(x, y) ((__typeof__(x))((y)-1))
xiaohu.huange7678d12022-05-10 00:56:48 +080085#define round_up(x, y) ((((x)-1) | __round_mask(x, y)) + 1)
Xiaohu.Huang83a0b702021-12-28 11:06:24 +080086#define round_down(x, y) ((x) & ~__round_mask(x, y))
87
88typedef uint64_t u64;
89typedef uint32_t u32;
90typedef uint16_t u16;
91typedef uint8_t u8;
92typedef int64_t s64;
93typedef int32_t s32;
94typedef int16_t s16;
95typedef int8_t s8;
96
97#ifndef BIT
98#define BIT(x) (1 << (x))
99#endif
100
101#ifdef __cplusplus
102}
103#endif
104#endif