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git.odroid.com / yocto / rtos_sdk / arch / riscv / refs/heads/odroidc5-v2023.01 / . / entry_wcn.S
blob: bb115bc8662ad386511f0fc7b1d7158d2030856b [file] [log] [blame]
xiaohu.huang797c4c12024-01-24 18:52:43 +0800[diff] [blame]1/*
2 * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: MIT
5 */
6
7#ifndef ENTRY_S
8#define ENTRY_S
9
10#include "riscv_encoding.h"
shijie.xiong1038db02024-02-01 14:16:05 +0800[diff] [blame]11#include "portContext.h"
xiaohu.huang797c4c12024-01-24 18:52:43 +0800[diff] [blame]12
13#if __riscv_xlen == 64
14#define SLL32 sllw
15#define STORE sd
16#define LOAD ld
17#define LWU lwu
18#define LOG_REGBYTES 3
19#else
20#define SLL32 sll
21#define STORE sw
22#define LOAD lw
23#define LWU lw
24#define LOG_REGBYTES 2
25#endif
26#define REGBYTES (1 << LOG_REGBYTES)
27
28#if __riscv_flen == 64
29#define FPSTORE fsd
30#define FPLOAD fld
31#define LOG_FPREGBYTES 3
32#else
33#define FPSTORE fsw
34#define FPLOAD flw
35#define LOG_FPREGBYTES 2
36#endif
37
38.align 2
39.extern interrupt_register_nmi
40.extern interrupt_register_exception
41
42.macro wr_reg, address, value
43 li t0, \address
44 li t1, \value
45 sw t1, (t0)
46.endm
47
48###############################################
49###############################################
xiaohu.huang797c4c12024-01-24 18:52:43 +0800[diff] [blame]50# Disable Interrupt
51#
52.macro DISABLE_MIE
53 csrc CSR_MSTATUS, MSTATUS_MIE
54.endm
55###############################################
56###############################################
57# Enable Interrupt
58#
59.macro ENABLE_MIE
60 csrs CSR_MSTATUS, MSTATUS_MIE
61.endm
62###############################################
63###############################################
shijie.xiong1038db02024-02-01 14:16:05 +0800[diff] [blame]64# save exception context
65.macro CONTEXT_SAVE_EXCEPTION_CONTEXT
66 portcontextSAVE_CONTEXT_INTERNAL
67 csrr a0, mcause
68 csrr a1, mepc
69 addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exception. */
70 store_x a1, 0( sp ) /* Save updated exception return address. */
71 mv a1, sp
72 load_x sp, xISRStackTop /* Switch to ISR stack. */
73.endm
74###############################################
75###############################################
76# restore exception context
77.macro CONTEXT_RESTORE_CONTEXT
78 portcontextRESTORE_CONTEXT
79.endm
80###############################################
81###############################################
xiaohu.huang797c4c12024-01-24 18:52:43 +0800[diff] [blame]82
83 .align 6
84 .global exception_entry
85exception_entry:
shijie.xiong1038db02024-02-01 14:16:05 +0800[diff] [blame]86 CONTEXT_SAVE_EXCEPTION_CONTEXT
xiaohu.huang797c4c12024-01-24 18:52:43 +0800[diff] [blame]87 call interrupt_register_exception
shijie.xiong1038db02024-02-01 14:16:05 +0800[diff] [blame]88 CONTEXT_RESTORE_CONTEXT
89
xiaohu.huang797c4c12024-01-24 18:52:43 +0800[diff] [blame]90 mret
91
92###############################################
93###############################################
94
95 .align 2
96 .global nmi_entry
97nmi_entry:
shijie.xiong1038db02024-02-01 14:16:05 +0800[diff] [blame]98 portcontextSAVE_INTERRUPT_CONTEXT
xiaohu.huang797c4c12024-01-24 18:52:43 +0800[diff] [blame]99 call interrupt_register_nmi
shijie.xiong1038db02024-02-01 14:16:05 +0800[diff] [blame]100 portcontextRESTORE_CONTEXT
101
xiaohu.huang797c4c12024-01-24 18:52:43 +0800[diff] [blame]102 mret
103
104###############################################
105###############################################
106
107 .align 2
108 .global int_entry
109int_entry:
shijie.xiong1038db02024-02-01 14:16:05 +0800[diff] [blame]110 portcontextSAVE_INTERRUPT_CONTEXT
xiaohu.huang797c4c12024-01-24 18:52:43 +0800[diff] [blame]111
112service_loop:
113 // Claim the CLIC to find its pending highest ID
114 // if the ID is not 0, then automatically enable the mstatus.MIE, and jump to its vector-entry-label
115 // and update the link register
116 csrrw ra, CSR_JALMNXTI, ra
117
xiaohu.huang797c4c12024-01-24 18:52:43 +0800[diff] [blame]118 #---- Critical section with interrupts disabled -----------------------
119 DISABLE_MIE # Disable interrupts
120
shijie.xiong1038db02024-02-01 14:16:05 +0800[diff] [blame]121 portcontextRESTORE_CONTEXT
xiaohu.huang797c4c12024-01-24 18:52:43 +0800[diff] [blame]122
xiaohu.huang797c4c12024-01-24 18:52:43 +0800[diff] [blame]123 // Return to regular code
124 mret
125
126#endif