| /* |
| * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved. |
| * |
| * SPDX-License-Identifier: MIT |
| */ |
| |
| #define NO_ENCT |
| #ifdef NO_ENCT |
| #undef ENCT_VFIFO2VD_CTL |
| #undef ENCT_VFIFO2VD_PIXEL_START |
| #undef ENCT_VFIFO2VD_PIXEL_END |
| #undef ENCT_VFIFO2VD_LINE_TOP_START |
| #undef ENCT_VFIFO2VD_LINE_TOP_END |
| #undef ENCT_VFIFO2VD_LINE_BOT_START |
| #undef ENCT_VFIFO2VD_LINE_BOT_END |
| #undef ENCT_VFIFO2VD_CTL2 |
| #undef ENCT_TST_EN |
| #undef ENCT_TST_MDSEL |
| #undef ENCT_TST_Y |
| #undef ENCT_TST_CB |
| #undef ENCT_TST_CR |
| #undef ENCT_TST_CLRBAR_STRT |
| #undef ENCT_TST_CLRBAR_WIDTH |
| #undef ENCT_TST_VDCNT_STSET |
| #undef ENCT_SYNC_LINE_LENGTH |
| #undef ENCT_SYNC_PIXEL_EN |
| #undef ENCT_SYNC_TO_LINE_EN |
| #undef ENCT_SYNC_TO_PIXEL |
| #undef ENCT_VIDEO_EN |
| #undef ENCT_VIDEO_Y_SCL |
| #undef ENCT_VIDEO_PB_SCL |
| #undef ENCT_VIDEO_PR_SCL |
| #undef ENCT_VIDEO_Y_OFFST |
| #undef ENCT_VIDEO_PB_OFFST |
| #undef ENCT_VIDEO_PR_OFFST |
| #undef ENCT_VIDEO_MODE |
| #undef ENCT_VIDEO_MODE_ADV |
| #undef ENCT_DBG_PX_RST |
| #undef ENCT_DBG_LN_RST |
| #undef ENCT_DBG_PX_INT |
| #undef ENCT_DBG_LN_INT |
| #undef ENCT_VIDEO_YFP1_HTIME |
| #undef ENCT_VIDEO_YFP2_HTIME |
| #undef ENCT_VIDEO_YC_DLY |
| #undef ENCT_VIDEO_MAX_PXCNT |
| #undef ENCT_VIDEO_HAVON_END |
| #undef ENCT_VIDEO_HAVON_BEGIN |
| #undef ENCT_VIDEO_VAVON_ELINE |
| #undef ENCT_VIDEO_VAVON_BLINE |
| #undef ENCT_VIDEO_HSO_BEGIN |
| #undef ENCT_VIDEO_HSO_END |
| #undef ENCT_VIDEO_VSO_BEGIN |
| #undef ENCT_VIDEO_VSO_END |
| #undef ENCT_VIDEO_VSO_BLINE |
| #undef ENCT_VIDEO_VSO_ELINE |
| #undef ENCT_VIDEO_MAX_LNCNT |
| #undef ENCT_VIDEO_BLANKY_VAL |
| #undef ENCT_VIDEO_BLANKPB_VAL |
| #undef ENCT_VIDEO_BLANKPR_VAL |
| #undef ENCT_VIDEO_HOFFST |
| #undef ENCT_VIDEO_VOFFST |
| #undef ENCT_VIDEO_RGB_CTRL |
| #undef ENCT_VIDEO_FILT_CTRL |
| #undef ENCT_VIDEO_OFLD_VPEQ_OFST |
| #undef ENCT_VIDEO_OFLD_VOAV_OFST |
| #undef ENCT_VIDEO_MATRIX_CB |
| #undef ENCT_VIDEO_MATRIX_CR |
| #undef ENCT_VIDEO_RGBIN_CTRL |
| #undef ENCT_MAX_LINE_SWITCH_POINT |
| #undef ENCT_DACSEL_0 |
| #undef ENCT_DACSEL_1 |
| // re-define |
| #define ENCT_VFIFO2VD_CTL ENCL_VFIFO2VD_CTL |
| #define ENCT_VFIFO2VD_PIXEL_START ENCL_VFIFO2VD_PIXEL_START |
| #define ENCT_VFIFO2VD_PIXEL_END ENCL_VFIFO2VD_PIXEL_END |
| #define ENCT_VFIFO2VD_LINE_TOP_START ENCL_VFIFO2VD_LINE_TOP_START |
| #define ENCT_VFIFO2VD_LINE_TOP_END ENCL_VFIFO2VD_LINE_TOP_END |
| #define ENCT_VFIFO2VD_LINE_BOT_START ENCL_VFIFO2VD_LINE_BOT_START |
| #define ENCT_VFIFO2VD_LINE_BOT_END ENCL_VFIFO2VD_LINE_BOT_END |
| #define ENCT_VFIFO2VD_CTL2 ENCL_VFIFO2VD_CTL2 |
| #define ENCT_TST_EN ENCL_TST_EN |
| #define ENCT_TST_MDSEL ENCL_TST_MDSEL |
| #define ENCT_TST_Y ENCL_TST_Y |
| #define ENCT_TST_CB ENCL_TST_CB |
| #define ENCT_TST_CR ENCL_TST_CR |
| #define ENCT_TST_CLRBAR_STRT ENCL_TST_CLRBAR_STRT |
| #define ENCT_TST_CLRBAR_WIDTH ENCL_TST_CLRBAR_WIDTH |
| #define ENCT_TST_VDCNT_STSET ENCL_TST_VDCNT_STSET |
| #define ENCT_SYNC_LINE_LENGTH ENCL_SYNC_LINE_LENGTH |
| #define ENCT_SYNC_PIXEL_EN ENCL_SYNC_PIXEL_EN |
| #define ENCT_SYNC_TO_LINE_EN ENCL_SYNC_TO_LINE_EN |
| #define ENCT_SYNC_TO_PIXEL ENCL_SYNC_TO_PIXEL |
| #define ENCT_VIDEO_EN ENCL_VIDEO_EN |
| #define ENCT_VIDEO_Y_SCL ENCL_VIDEO_Y_SCL |
| #define ENCT_VIDEO_PB_SCL ENCL_VIDEO_PB_SCL |
| #define ENCT_VIDEO_PR_SCL ENCL_VIDEO_PR_SCL |
| #define ENCT_VIDEO_Y_OFFST ENCL_VIDEO_Y_OFFST |
| #define ENCT_VIDEO_PB_OFFST ENCL_VIDEO_PB_OFFST |
| #define ENCT_VIDEO_PR_OFFST ENCL_VIDEO_PR_OFFST |
| #define ENCT_VIDEO_MODE ENCL_VIDEO_MODE |
| #define ENCT_VIDEO_MODE_ADV ENCL_VIDEO_MODE_ADV |
| #define ENCT_DBG_PX_RST ENCL_DBG_PX_RST |
| #define ENCT_DBG_LN_RST ENCL_DBG_LN_RST |
| #define ENCT_DBG_PX_INT ENCL_DBG_PX_INT |
| #define ENCT_DBG_LN_INT ENCL_DBG_LN_INT |
| #define ENCT_VIDEO_YFP1_HTIME ENCL_VIDEO_YFP1_HTIME |
| #define ENCT_VIDEO_YFP2_HTIME ENCL_VIDEO_YFP2_HTIME |
| #define ENCT_VIDEO_YC_DLY ENCL_VIDEO_YC_DLY |
| #define ENCT_VIDEO_MAX_PXCNT ENCL_VIDEO_MAX_PXCNT |
| #define ENCT_VIDEO_HAVON_END ENCL_VIDEO_HAVON_END |
| #define ENCT_VIDEO_HAVON_BEGIN ENCL_VIDEO_HAVON_BEGIN |
| #define ENCT_VIDEO_VAVON_ELINE ENCL_VIDEO_VAVON_ELINE |
| #define ENCT_VIDEO_VAVON_BLINE ENCL_VIDEO_VAVON_BLINE |
| #define ENCT_VIDEO_HSO_BEGIN ENCL_VIDEO_HSO_BEGIN |
| #define ENCT_VIDEO_HSO_END ENCL_VIDEO_HSO_END |
| #define ENCT_VIDEO_VSO_BEGIN ENCL_VIDEO_VSO_BEGIN |
| #define ENCT_VIDEO_VSO_END ENCL_VIDEO_VSO_END |
| #define ENCT_VIDEO_VSO_BLINE ENCL_VIDEO_VSO_BLINE |
| #define ENCT_VIDEO_VSO_ELINE ENCL_VIDEO_VSO_ELINE |
| #define ENCT_VIDEO_MAX_LNCNT ENCL_VIDEO_MAX_LNCNT |
| #define ENCT_VIDEO_BLANKY_VAL ENCL_VIDEO_BLANKY_VAL |
| #define ENCT_VIDEO_BLANKPB_VAL ENCL_VIDEO_BLANKPB_VAL |
| #define ENCT_VIDEO_BLANKPR_VAL ENCL_VIDEO_BLANKPR_VAL |
| #define ENCT_VIDEO_HOFFST ENCL_VIDEO_HOFFST |
| #define ENCT_VIDEO_VOFFST ENCL_VIDEO_VOFFST |
| #define ENCT_VIDEO_RGB_CTRL ENCL_VIDEO_RGB_CTRL |
| #define ENCT_VIDEO_FILT_CTRL ENCL_VIDEO_FILT_CTRL |
| #define ENCT_VIDEO_OFLD_VPEQ_OFST ENCL_VIDEO_OFLD_VPEQ_OFST |
| #define ENCT_VIDEO_OFLD_VOAV_OFST ENCL_VIDEO_OFLD_VOAV_OFST |
| #define ENCT_VIDEO_MATRIX_CB ENCL_VIDEO_MATRIX_CB |
| #define ENCT_VIDEO_MATRIX_CR ENCL_VIDEO_MATRIX_CR |
| #define ENCT_VIDEO_RGBIN_CTRL ENCL_VIDEO_RGBIN_CTRL |
| #define ENCT_MAX_LINE_SWITCH_POINT ENCL_MAX_LINE_SWITCH_POINT |
| #define ENCT_DACSEL_0 ENCL_DACSEL_0 |
| #define ENCT_DACSEL_1 ENCL_DACSEL_1 |
| |
| #undef GAMMA_CNTL_PORT |
| #undef GAMMA_DATA_PORT |
| #undef GAMMA_ADDR_PORT |
| #undef GAMMA_VCOM_HSWITCH_ADDR |
| #undef RGB_BASE_ADDR |
| #undef RGB_COEFF_ADDR |
| #undef POL_CNTL_ADDR |
| #undef DITH_CNTL_ADDR |
| #undef GAMMA_PROBE_CTRL |
| #undef GAMMA_PROBE_COLOR_L |
| #undef GAMMA_PROBE_COLOR_H |
| #undef GAMMA_PROBE_HL_COLOR |
| #undef GAMMA_PROBE_POS_X |
| #undef GAMMA_PROBE_POS_Y |
| #undef STH1_HS_ADDR |
| #undef STH1_HE_ADDR |
| #undef STH1_VS_ADDR |
| #undef STH1_VE_ADDR |
| #undef STH2_HS_ADDR |
| #undef STH2_HE_ADDR |
| #undef STH2_VS_ADDR |
| #undef STH2_VE_ADDR |
| #undef OEH_HS_ADDR |
| #undef OEH_HE_ADDR |
| #undef OEH_VS_ADDR |
| #undef OEH_VE_ADDR |
| #undef VCOM_HSWITCH_ADDR |
| #undef VCOM_VS_ADDR |
| #undef VCOM_VE_ADDR |
| #undef CPV1_HS_ADDR |
| #undef CPV1_HE_ADDR |
| #undef CPV1_VS_ADDR |
| #undef CPV1_VE_ADDR |
| #undef CPV2_HS_ADDR |
| #undef CPV2_HE_ADDR |
| #undef CPV2_VS_ADDR |
| #undef CPV2_VE_ADDR |
| #undef STV1_HS_ADDR |
| #undef STV1_HE_ADDR |
| #undef STV1_VS_ADDR |
| #undef STV1_VE_ADDR |
| #undef STV2_HS_ADDR |
| #undef STV2_HE_ADDR |
| #undef STV2_VS_ADDR |
| #undef STV2_VE_ADDR |
| #undef OEV1_HS_ADDR |
| #undef OEV1_HE_ADDR |
| #undef OEV1_VS_ADDR |
| #undef OEV1_VE_ADDR |
| #undef OEV2_HS_ADDR |
| #undef OEV2_HE_ADDR |
| #undef OEV2_VS_ADDR |
| #undef OEV2_VE_ADDR |
| #undef OEV3_HS_ADDR |
| #undef OEV3_HE_ADDR |
| #undef OEV3_VS_ADDR |
| #undef OEV3_VE_ADDR |
| #undef LCD_PWR_ADDR |
| #undef LCD_PWM0_LO_ADDR |
| #undef LCD_PWM0_HI_ADDR |
| #undef LCD_PWM1_LO_ADDR |
| #undef LCD_PWM1_HI_ADDR |
| #undef INV_CNT_ADDR |
| #undef TCON_MISC_SEL_ADDR |
| #undef DUAL_PORT_CNTL_ADDR |
| #undef TCON_DOUBLE_CTL |
| #undef TCON_PATTERN_HI |
| #undef TCON_PATTERN_LO |
| #undef DE_HS_ADDR |
| #undef DE_HE_ADDR |
| #undef DE_VS_ADDR |
| #undef DE_VE_ADDR |
| #undef HSYNC_HS_ADDR |
| #undef HSYNC_HE_ADDR |
| #undef HSYNC_VS_ADDR |
| #undef HSYNC_VE_ADDR |
| #undef VSYNC_HS_ADDR |
| #undef VSYNC_HE_ADDR |
| #undef VSYNC_VS_ADDR |
| #undef VSYNC_VE_ADDR |
| #undef LCD_MCU_CTL |
| |
| #define GAMMA_CNTL_PORT L_GAMMA_CNTL_PORT |
| #define GAMMA_DATA_PORT L_GAMMA_DATA_PORT |
| #define GAMMA_ADDR_PORT L_GAMMA_ADDR_PORT |
| #define GAMMA_VCOM_HSWITCH_ADDR L_GAMMA_VCOM_HSWITCH_ADDR |
| #define RGB_BASE_ADDR L_RGB_BASE_ADDR |
| #define RGB_COEFF_ADDR L_RGB_COEFF_ADDR |
| #define POL_CNTL_ADDR L_POL_CNTL_ADDR |
| #define DITH_CNTL_ADDR L_DITH_CNTL_ADDR |
| #define GAMMA_PROBE_CTRL L_GAMMA_PROBE_CTRL |
| #define GAMMA_PROBE_COLOR_L L_GAMMA_PROBE_COLOR_L |
| #define GAMMA_PROBE_COLOR_H L_GAMMA_PROBE_COLOR_H |
| #define GAMMA_PROBE_HL_COLOR L_GAMMA_PROBE_HL_COLOR |
| #define GAMMA_PROBE_POS_X L_GAMMA_PROBE_POS_X |
| #define GAMMA_PROBE_POS_Y L_GAMMA_PROBE_POS_Y |
| #define STH1_HS_ADDR L_STH1_HS_ADDR |
| #define STH1_HE_ADDR L_STH1_HE_ADDR |
| #define STH1_VS_ADDR L_STH1_VS_ADDR |
| #define STH1_VE_ADDR L_STH1_VE_ADDR |
| #define STH2_HS_ADDR L_STH2_HS_ADDR |
| #define STH2_HE_ADDR L_STH2_HE_ADDR |
| #define STH2_VS_ADDR L_STH2_VS_ADDR |
| #define STH2_VE_ADDR L_STH2_VE_ADDR |
| #define OEH_HS_ADDR L_OEH_HS_ADDR |
| #define OEH_HE_ADDR L_OEH_HE_ADDR |
| #define OEH_VS_ADDR L_OEH_VS_ADDR |
| #define OEH_VE_ADDR L_OEH_VE_ADDR |
| #define VCOM_HSWITCH_ADDR L_VCOM_HSWITCH_ADDR |
| #define VCOM_VS_ADDR L_VCOM_VS_ADDR |
| #define VCOM_VE_ADDR L_VCOM_VE_ADDR |
| #define CPV1_HS_ADDR L_CPV1_HS_ADDR |
| #define CPV1_HE_ADDR L_CPV1_HE_ADDR |
| #define CPV1_VS_ADDR L_CPV1_VS_ADDR |
| #define CPV1_VE_ADDR L_CPV1_VE_ADDR |
| #define CPV2_HS_ADDR L_CPV2_HS_ADDR |
| #define CPV2_HE_ADDR L_CPV2_HE_ADDR |
| #define CPV2_VS_ADDR L_CPV2_VS_ADDR |
| #define CPV2_VE_ADDR L_CPV2_VE_ADDR |
| #define STV1_HS_ADDR L_STV1_HS_ADDR |
| #define STV1_HE_ADDR L_STV1_HE_ADDR |
| #define STV1_VS_ADDR L_STV1_VS_ADDR |
| #define STV1_VE_ADDR L_STV1_VE_ADDR |
| #define STV2_HS_ADDR L_STV2_HS_ADDR |
| #define STV2_HE_ADDR L_STV2_HE_ADDR |
| #define STV2_VS_ADDR L_STV2_VS_ADDR |
| #define STV2_VE_ADDR L_STV2_VE_ADDR |
| #define OEV1_HS_ADDR L_OEV1_HS_ADDR |
| #define OEV1_HE_ADDR L_OEV1_HE_ADDR |
| #define OEV1_VS_ADDR L_OEV1_VS_ADDR |
| #define OEV1_VE_ADDR L_OEV1_VE_ADDR |
| #define OEV2_HS_ADDR L_OEV2_HS_ADDR |
| #define OEV2_HE_ADDR L_OEV2_HE_ADDR |
| #define OEV2_VS_ADDR L_OEV2_VS_ADDR |
| #define OEV2_VE_ADDR L_OEV2_VE_ADDR |
| #define OEV3_HS_ADDR L_OEV3_HS_ADDR |
| #define OEV3_HE_ADDR L_OEV3_HE_ADDR |
| #define OEV3_VS_ADDR L_OEV3_VS_ADDR |
| #define OEV3_VE_ADDR L_OEV3_VE_ADDR |
| #define LCD_PWR_ADDR L_LCD_PWR_ADDR |
| #define LCD_PWM0_LO_ADDR L_LCD_PWM0_LO_ADDR |
| #define LCD_PWM0_HI_ADDR L_LCD_PWM0_HI_ADDR |
| #define LCD_PWM1_LO_ADDR L_LCD_PWM1_LO_ADDR |
| #define LCD_PWM1_HI_ADDR L_LCD_PWM1_HI_ADDR |
| #define INV_CNT_ADDR L_INV_CNT_ADDR |
| #define TCON_MISC_SEL_ADDR L_TCON_MISC_SEL_ADDR |
| #define DUAL_PORT_CNTL_ADDR L_DUAL_PORT_CNTL_ADDR |
| #define TCON_DOUBLE_CTL L_TCON_DOUBLE_CTL |
| #define TCON_PATTERN_HI L_TCON_PATTERN_HI |
| #define TCON_PATTERN_LO L_TCON_PATTERN_LO |
| #define DE_HS_ADDR L_DE_HS_ADDR |
| #define DE_HE_ADDR L_DE_HE_ADDR |
| #define DE_VS_ADDR L_DE_VS_ADDR |
| #define DE_VE_ADDR L_DE_VE_ADDR |
| #define HSYNC_HS_ADDR L_HSYNC_HS_ADDR |
| #define HSYNC_HE_ADDR L_HSYNC_HE_ADDR |
| #define HSYNC_VS_ADDR L_HSYNC_VS_ADDR |
| #define HSYNC_VE_ADDR L_HSYNC_VE_ADDR |
| #define VSYNC_HS_ADDR L_VSYNC_HS_ADDR |
| #define VSYNC_HE_ADDR L_VSYNC_HE_ADDR |
| #define VSYNC_VS_ADDR L_VSYNC_VS_ADDR |
| #define VSYNC_VE_ADDR L_VSYNC_VE_ADDR |
| #define LCD_MCU_CTL L_LCD_MCU_CTL |
| |
| #endif |