blob: 8210e8f503554b52824b91fac2f1e90ede07d220 [file] [log] [blame]
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
4 */
5
6#include <common.h>
7#include <command.h>
8#include <env.h>
9#include <malloc.h>
10#include <asm/byteorder.h>
11#include <amlogic/clk_measure.h>
12#include <amlogic/media/vout/hdmitx21/hdmitx.h>
Wenjie Qiao389d3ea2023-05-25 16:07:03 +080013#include <linux/delay.h>
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +080014#include <image.h>
Wenjie Qiao8a73a562023-02-23 18:37:14 +080015#include <amlogic/media/dv/dolby_vision.h>
16#include <linux/libfdt_env.h>
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +080017#include <amlogic/media/vout/dsc.h>
xiang.wu114497ab2024-02-21 14:57:05 +080018#include <amlogic/media/vout/aml_vinfo.h>
19#include <linux/arm-smccc.h>
Wenjie Qiao8a73a562023-02-23 18:37:14 +080020
21static unsigned char edid_raw_buf[512] = {0};
Wenjie Qiao389d3ea2023-05-25 16:07:03 +080022/* there may be outputmode/2/3 when in multi-display case,
23 * sel_hdmimode is used to save the selected hdmi mode
24 */
25static char sel_hdmimode[MODE_LEN] = {0};
Wenjie Qiao8a73a562023-02-23 18:37:14 +080026
27static void dump_full_edid(const unsigned char *buf)
28{
29 int i;
30 int blk_no;
31
32 if (!buf)
33 return;
34 blk_no = buf[126] + 1;
35 if (blk_no > 4)
36 blk_no = 4;
Wenjie Qiao389d3ea2023-05-25 16:07:03 +080037
38 if (blk_no == 2)
39 if (buf[128 + 4] == 0xe2 && buf[128 + 5] == 0x78)
40 blk_no = buf[128 + 6] + 1;
xiang.wu114497ab2024-02-21 14:57:05 +080041 if (blk_no > EDID_MAX_BLOCK)
42 blk_no = EDID_MAX_BLOCK;
Wenjie Qiao389d3ea2023-05-25 16:07:03 +080043
Wenjie Qiao8a73a562023-02-23 18:37:14 +080044 printf("dump EDID rawdata\n");
45 printf(" ");
46 for (i = 0; i < blk_no * EDID_BLK_SIZE; i++)
47 printf("%02x", buf[i]);
48 printf("\n");
49}
50
51static int do_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
52{
53 unsigned char st = 0;
54 struct hdmitx_dev *hdev = get_hdmitx21_device();
55
56 memset(edid_raw_buf, 0, ARRAY_SIZE(edid_raw_buf));
57
58 st = hdev->hwop.read_edid(edid_raw_buf);
59
60 if (!st)
61 printf("edid read failed\n");
62
63 return st;
64}
65
66static int do_rx_det(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
67{
68 unsigned char st = 0;
69 struct hdmitx_dev *hdev = get_hdmitx21_device();
70
71 memset(edid_raw_buf, 0, ARRAY_SIZE(edid_raw_buf));
72
73 // read edid raw data
74 // current only support read 1 byte edid data
75 st = hdev->hwop.read_edid(edid_raw_buf);
76
77 if (st) {
78 if (edid_raw_buf[250] == 0xfb && edid_raw_buf[251] == 0x0c) {
79 printf("RX is FBC\n");
80
81 // set outputmode ENV
82 switch (edid_raw_buf[252] & 0x0f) {
83 case 0x0:
84 run_command("setenv outputmode 1080p50hz", 0);
85 break;
86 case 0x1:
87 run_command("setenv outputmode 2160p50hz420", 0);
88 break;
89 case 0x2:
90 run_command("setenv outputmode 1080p50hz44410bit", 0);
91 break;
92 case 0x3:
93 run_command("setenv outputmode 2160p50hz42010bit", 0);
94 break;
95 case 0x4:
96 run_command("setenv outputmode 2160p50hz42210bit", 0);
97 break;
98 case 0x5:
99 run_command("setenv outputmode 2160p50hz", 0);
100 break;
101 default:
102 run_command("setenv outputmode 1080p50hz", 0);
103 break;
104 }
105
106 /*et RX 3D Info*/
107 switch ((edid_raw_buf[252] >> 4) & 0x0f) {
108 case 0x00:
109 run_command("setenv rx_3d_info 0", 0);
110 break;
111 case 0x01:
112 run_command("setenv rx_3d_info 1", 0);
113 break;
114 case 0x02:
115 run_command("setenv rx_3d_info 2", 0);
116 break;
117 case 0x03:
118 run_command("setenv rx_3d_info 3", 0);
119 break;
120 case 0x04:
121 run_command("setenv rx_3d_info 4", 0);
122 break;
123 default:
124 break;
125 }
126
127 switch (edid_raw_buf[253]) {
128 case 0x1:
129 /*TODO*/
130 break;
131 case 0x2:
132 /*TODO*/
133 break;
134 default:
135 break;
136 }
137 }
138 } else {
139 printf("edid read failed\n");
140 }
141
142 return st;
143}
144
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800145static void save_default_720p(void)
146{
147 memcpy(sel_hdmimode, DEFAULT_HDMI_MODE, sizeof(DEFAULT_HDMI_MODE));
148 if (is_hdmi_mode(env_get("outputmode")))
149 env_set("outputmode", DEFAULT_HDMI_MODE);
150 else if (is_hdmi_mode(env_get("outputmode2")))
151 env_set("outputmode2", DEFAULT_HDMI_MODE);
152 else if (is_hdmi_mode(env_get("outputmode3")))
153 env_set("outputmode3", DEFAULT_HDMI_MODE);
154 env_set("colorattribute", DEFAULT_COLOR_FORMAT);
155}
156
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800157static void hdmitx_mask_rx_info(struct hdmitx_dev *hdev)
158{
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800159 if (!hdev || !hdev->para)
160 return;
161
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800162 if (env_get("colorattribute"))
163 hdmitx21_get_fmtpara(sel_hdmimode, env_get("colorattribute"));
164
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800165 /* when current output color depth is 8bit, mask hdr capability */
166 /* refer to SWPL-44445 for more detail */
167 if (hdev->para->cd == COLORDEPTH_24B)
168 memset(&hdev->RXCap.hdr_info, 0, sizeof(struct hdr_info));
169}
170
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800171/* If environment qms_en is true, and RX supports QMS, and the
172 * output mode is BRR then enable TX QMS
173 */
174static void qms_scene_pre_process(struct hdmitx_dev *hdev)
175{
176 bool env_qms_en = 0;
177 bool rx_qms_cap = 0;
178 enum hdmi_vic qms_brr_vic = HDMI_UNKNOWN;
179 const struct hdmi_timing *t = NULL;
180 char *color = NULL;
zongdong.jiao1ac547f2024-03-06 13:43:31 +0800181 const char *i_modes[3] = {
182 "480i", "576i", "1080i",
183 };
184 char *mode;
185 int i;
186
187 /* if current mode is interlaced mode, then skip QMS */
188 mode = env_get("hdmi_mode");
189 if (!mode)
190 return;
191 for (i = 0; i < 3; i++) {
192 if (strstr(mode, i_modes[i]))
193 return;
194 }
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800195
196 /* check uboot environment */
197 if (env_get("qms_en") && (env_get_ulong("qms_en", 10, 0) == 1))
198 env_qms_en = 1;
199
200 rx_qms_cap = hdev->RXCap.qms;
201
202 qms_brr_vic = hdmitx_find_brr_vic(hdev->vic);
203
204 if (env_qms_en && rx_qms_cap && qms_brr_vic != HDMI_UNKNOWN)
205 hdev->qms_en = 1;
206 pr_info("QMS: env %d rx %d vic %d brr_vic %d\n", env_qms_en, rx_qms_cap,
207 hdev->vic, qms_brr_vic);
208 if (!hdev->qms_en)
209 return;
210 hdev->brr_vic = qms_brr_vic;
211 /* save brr_vic to vic without the environment */
212 hdev->vic = hdev->brr_vic;
213 /* reconfig the hdmi para */
214 t = hdmitx21_gettiming_from_vic(hdev->brr_vic);
215 if (!t) {
216 pr_info("not find brr_vic %d timing\n", hdev->brr_vic);
217 return;
218 }
219 color = env_get("user_colorattribute");
xiang.wu16ac2bda2024-05-08 10:54:25 +0800220 if (!color || !strcmp(color, "none"))
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800221 color = env_get("colorattribute");
222 hdev->para = hdmitx21_get_fmtpara(t->sname ? t->sname : t->name, color);
223}
224
225static void qms_scene_post_process(struct hdmitx_dev *hdev)
226{
227 // Init QMS parameter
228 vrr_init_qms_para(hdev);
229}
230
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800231static int do_output(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
232{
233 const struct hdmi_timing *timing = NULL;
234 struct hdmitx_dev *hdev = get_hdmitx21_device();
235
xiang.wu1a6d6f1d2023-08-04 14:13:00 +0800236#ifdef CONFIG_PXP_EMULATOR
237 hdmitx21_pxp_init(1);
238#endif
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800239 if (argc < 1)
240 return cmd_usage(cmdtp);
241
242 if (strcmp(argv[1], "list") == 0) {
243 hdev->hwop.list_support_modes();
244 } else if (strcmp(argv[1], "bist") == 0) {
245 unsigned int mode = 0;
246
247 if (strcmp(argv[2], "off") == 0)
248 mode = 0;
249 else if (strcmp(argv[2], "line") == 0)
250 mode = 2;
251 else if (strcmp(argv[2], "dot") == 0)
252 mode = 3;
253 else if (strcmp(argv[2], "x") == 0)
254 mode = 'x';
255 else if (strcmp(argv[2], "X") == 0)
256 mode = 'X';
257 else
258 mode = simple_strtoul(argv[2], NULL, 10);
259 hdev->hwop.test_bist(mode);
260 } else if (strcmp(argv[1], "prbs") == 0) {
261 hdev->para->cs = HDMI_COLORSPACE_RGB;
262 hdev->para->cd = COLORDEPTH_24B;
263 hdev->vic = HDMI_16_1920x1080p60_16x9;
264 hdmitx21_set(hdev);
265 hdev->hwop.test_prbs();
266 } else if (strncmp(argv[1], "div40", 5) == 0) {
267 bool div40 = 0;
268
269 if (argv[1][5] == '1')
270 div40 = 1;
271 hdev->hwop.set_div40(div40);
272 } else { /* "output" */
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800273 if (!hdev->pxp_mode) {
xiang.wu114497ab2024-02-21 14:57:05 +0800274 if (!hdmitx_edid_check_data_valid(0, hdev->rawedid)) {
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800275 /* in SWPL-34712: if EDID parsing error in kernel,
276 * only forcely output default mode(480p,RGB,8bit)
277 * in sysctl, not save the default mode to env.
278 * if uboot follow this rule, will cause issue OTT-19333:
279 * uboot read edid error and then output default mode,
280 * without save it mode env. if then kernel edid normal,
281 * sysctrl/kernel get mode from env, the actual output
282 * mode differs with outputmode env,it will
283 * cause display abnormal(such as stretch). so don't
284 * follow this rule in uboot, that's to say the actual
285 * output mode needs to stays with the outputmode env.
286 */
287 printf("edid parsing ng, forcely output 720p, rgb,8bit\n");
288 save_default_720p();
289 hdev->vic = HDMI_4_1280x720p60_16x9;
290 hdev->para =
291 hdmitx21_get_fmtpara("720p60hz", "rgb,8bit");
292 hdev->para->cs = HDMI_COLORSPACE_RGB;
293 hdev->para->cd = COLORDEPTH_24B;
294 hdmitx21_set(hdev);
295 return CMD_RET_SUCCESS;
296 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800297 }
298 if (!env_get("colorattribute"))
299 env_set("colorattribute", "444,8bit");
300 hdev->para = hdmitx21_get_fmtpara(argv[1], env_get("colorattribute"));
301 hdev->vic = hdev->para->timing.vic;
xiang.wu114497ab2024-02-21 14:57:05 +0800302 if (hdev->vic == HDMI_0_UNKNOWN) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800303 /* Not find VIC */
304 printf("Not find '%s' mapped VIC\n", argv[1]);
305 return CMD_RET_FAILURE;
306 }
307 if (strstr(argv[1], "hz420"))
308 hdev->para->cs = HDMI_COLORSPACE_YUV420;
309 /* S5 support over 6G, T7 not support */
310 switch (hdev->vic) {
311 case HDMI_96_3840x2160p50_16x9:
312 case HDMI_97_3840x2160p60_16x9:
313 case HDMI_101_4096x2160p50_256x135:
314 case HDMI_102_4096x2160p60_256x135:
315 case HDMI_106_3840x2160p50_64x27:
316 case HDMI_107_3840x2160p60_64x27:
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800317 if (hdev->chip_type != MESON_CPU_ID_S5) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800318 if (hdev->para->cs == HDMI_COLORSPACE_RGB ||
319 hdev->para->cs == HDMI_COLORSPACE_YUV444) {
320 if (hdev->para->cd != COLORDEPTH_24B) {
321 printf("vic %d cs %d has no cd %d\n",
322 hdev->vic,
323 hdev->para->cs,
324 hdev->para->cd);
325 hdev->para->cd = COLORDEPTH_24B;
326 printf("set cd as %d\n", COLORDEPTH_24B);
327 }
328 }
329 }
330 break;
331 default:
332 /* In Spec2.1 Table 7-34, greater than 2160p30hz will support y420 */
333 timing = hdmitx21_gettiming_from_vic(hdev->vic);
334 if (!timing)
335 break;
336 if (timing->v_active > 2160 && timing->v_freq > 30000)
337 break;
338 if (timing->v_active >= 4320)
339 break;
340 if (hdev->para->cs == HDMI_COLORSPACE_YUV420) {
341 printf("vic %d has no cs %d\n", hdev->vic,
342 hdev->para->cs);
343 hdev->para->cs = HDMI_COLORSPACE_YUV444;
344 printf("set cs as %d\n", HDMI_COLORSPACE_YUV444);
345 }
346 break;
347 }
348 printf("set hdmitx VIC = %d CS = %d CD = %d\n",
349 hdev->vic, hdev->para->cs, hdev->para->cd);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800350 qms_scene_pre_process(hdev);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800351 /* currently, hdmi mode is always set, if
352 * mode set abort/exit, need to add return
353 * result of mode setting, so that vout
354 * driver will pass it to kernel, and do
355 * mode setting again when vout init in kernel
356 */
357 hdmitx21_set(hdev);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800358 qms_scene_post_process(hdev);
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800359 if (hdev->frl_rate && !hdev->flt_train_st) {
360 /* FLT training failed, need go to tmds mode */
361 printf("hdmitx frl training failed, set tmds mode\n");
362 run_command("setenv hdmimode 1080p60hz", 0);
363 run_command("setenv colorattribute 422,12bit", 0);
364 run_command("run init_display_base", 0);
365 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800366 }
367 return CMD_RET_SUCCESS;
368}
369
370static int do_clkmsr(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
371{
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800372 struct hdmitx_dev *hdev = get_hdmitx21_device();
373
374 if (hdev->chip_type == MESON_CPU_ID_S5) {
375 clk_msr(4);
376 clk_msr(8);
377 clk_msr(16);
378 clk_msr(27);
379 clk_msr(63);
380 clk_msr(64);
381 clk_msr(66);
382 clk_msr(68);
383 clk_msr(69);
384 clk_msr(70);
385 clk_msr(71);
386 clk_msr(72);
387 clk_msr(73);
388 clk_msr(74);
389 clk_msr(75);
390 clk_msr(76);
391 clk_msr(79);
392 clk_msr(82);
393 clk_msr(89);
394 clk_msr(90);
395 clk_msr(91);
396 clk_msr(92);
397 clk_msr(93);
398 clk_msr(94);
399 clk_msr(95);
400 return CMD_RET_SUCCESS;
401 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800402 clk_msr(51);
403 clk_msr(59);
404 clk_msr(61);
405 clk_msr(76);
406 clk_msr(77);
407 clk_msr(78);
408 clk_msr(80);
409 clk_msr(81);
410 clk_msr(82);
411 clk_msr(83);
412 clk_msr(219);
413 clk_msr(220);
414 clk_msr(221);
415 clk_msr(222);
416 return CMD_RET_SUCCESS;
417}
418
419static int do_blank(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
420{
421 struct hdmitx_dev *hdev = get_hdmitx21_device();
422
423 if (argc < 1)
424 return cmd_usage(cmdtp);
425
426 if (strcmp(argv[1], "1") == 0)
427 hdev->hwop.output_blank(1);
428 if (strcmp(argv[1], "0") == 0)
429 hdev->hwop.output_blank(0);
430
431 return CMD_RET_SUCCESS;
432}
433
434static int do_off(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
435{
436 struct hdmitx_dev *hdev = get_hdmitx21_device();
437
xiang.wu114497ab2024-02-21 14:57:05 +0800438 hdev->vic = HDMI_0_UNKNOWN;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800439 if (hdev->chip_type == MESON_CPU_ID_S5)
440 hdmitx_module_disable();
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800441 hdev->hwop.turn_off();
442 printf("turn off hdmitx\n");
443 return 1;
444}
445
446static int do_dump(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
447{
448 struct hdmitx_dev *hdev = get_hdmitx21_device();
449
450 hdev->hwop.dump_regs();
451 return 1;
452}
453
454static int do_reg(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
455{
456 unsigned long addr = 0;
457 unsigned int data = 0;
458
459 if (argc < 1)
460 return cmd_usage(cmdtp);
461
462 if (strncmp(argv[1], "rh", 2) == 0) {
463 addr = strtoul(argv[1] + 2, NULL, 16);
464 data = hdmitx21_rd_reg((unsigned int)addr);
465 printf("rd[0x%lx] 0x%x\n", addr, data);
466 }
467
468 if (strncmp(argv[1], "wh", 2) == 0) {
469 addr = strtoul(argv[1] + 2, NULL, 16);
470 data = strtoul(argv[2], NULL, 16);
471 hdmitx21_wr_reg(addr, data);
472 printf("wr[0x%lx] 0x%x\n", addr, data);
473 }
474
475 return 1;
476}
477
xiang.wu1a6d6f1d2023-08-04 14:13:00 +0800478static int do_pbist(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
479{
480 struct hdmitx_dev *hdev = get_hdmitx21_device();
481
482 if (strcmp(argv[1], "1") == 0)
483 hdmitx21_pbist_config(hdev, hdev->vic, 1);
484 if (strcmp(argv[1], "0") == 0)
485 hdmitx21_pbist_config(hdev, hdev->vic, 0);
486 return 1;
487}
488
xiang.wu1492f3642024-01-08 14:06:40 +0800489static int do_s7_clk_config(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
490{
491 struct hdmitx_dev *hdev = get_hdmitx21_device();
492
493 if (strcmp(argv[1], "1") == 0) {
494 hdev->s7_clk_config = 1;
495 pr_info("s7_clk_config = %d\n", hdev->s7_clk_config);
496 } if (strcmp(argv[1], "0") == 0) {
497 hdev->s7_clk_config = 0;
498 pr_info("s7_clk_config = %d\n", hdev->s7_clk_config);
499 }
500 return 1;
501}
502
xiang.wu114497ab2024-02-21 14:57:05 +0800503static int get_rterm(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
504{
505 struct arm_smccc_res res;
506 u8 rterm_efuse;
507
508 arm_smccc_smc(HDCPTX_IOOPR, HDMITX_GET_RTERM, 0, 0, 0, 0, 0, 0, &res);
509 rterm_efuse = (unsigned int)((res.a0) & 0xffffffff);
510 pr_info("rterm_efuse = %d\n", rterm_efuse);
511 return 1;
512}
513
xiang.wu1a6d6f1d2023-08-04 14:13:00 +0800514static int do_debug(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
515{
516 unsigned int enable_all = 0;
517 int pkt_op = 0;
518 unsigned int mov_val = 0;
519 unsigned char pb[28] = {0x46, 0xD0, 0x00, 0x00, 0x00, 0x00, 0x46, 0xD0,
520 0x00, 0x10, 0x21, 0xaa, 0x9b, 0x96, 0x19, 0xfc, 0x19, 0x75, 0xd5, 0x78,
521 0x10, 0x21, 0xaa, 0x9b, 0x96, 0x19, 0xfc, 0x19};
522 unsigned char hb[3] = {0x01, 0x02, 0x03};
523
524 if (argc < 1)
525 return cmd_usage(cmdtp);
526
527 if (strncmp(argv[1], "pkt", 3) == 0) {
528 enable_all = strtoul(argv[1] + 3, NULL, 16);
529 pkt_op = strtoul(argv[2], NULL, 16);
530 mov_val = strtoul(argv[3], NULL, 10);
531 pkt_send_position_change(enable_all, pkt_op, mov_val);
532 } else if (strncmp(argv[1], "w_dhdr", 6) == 0 ) {
533 hdmitx21_write_dhdr_sram();
534 } else if (strncmp(argv[1], "r_dhdr", 6) == 0 ) {
535 hdmitx21_read_dhdr_sram();
536 } else if (strncmp(argv[1], "t_avi", 4) == 0 ) {
537 printf("test send avi pkt\n");
538 hdmi_avi_infoframe_rawset(hb, pb);
539 } else if (strncmp(argv[1], "t_audio", 7) == 0 ) {
540 printf("test send audio pkt\n");
541 hdmi_audio_infoframe_rawset(hb, pb);
542 } else if (strncmp(argv[1], "t_sbtm", 6) == 0 ) {
543 printf("test send SBTM pkt\n");
544 hdmitx21_send_sbtm_pkt();
545 }
546
547 return 1;
548}
549
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800550static bool check_vic_exist(struct hdmitx_dev *hdev, enum hdmi_vic vic,
551 int count)
552{
553 struct rx_cap *rxcap = NULL;
554 int i;
555
556 rxcap = &hdev->RXCap;
557 for (i = 0; i < count; i++)
558 if (vic == rxcap->VIC[i])
559 return 1;
560
561 return 0;
562}
563
564static void disp_cap_show(struct hdmitx_dev *hdev)
565{
566 struct rx_cap *rxcap = NULL;
567 const struct hdmi_timing *timing = NULL;
568 enum hdmi_vic vic;
569 int i;
zhou.hana8e91612024-04-28 14:56:45 +0000570 enum hdmi_vic prefer_vic = HDMI_UNKNOWN;
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800571
572 if (!hdev)
573 return;
574
575 rxcap = &hdev->RXCap;
576 printf("disp_cap\n");
577 for (i = 0; i < rxcap->VIC_count && i < VIC_MAX_NUM; i++) {
578 vic = rxcap->VIC[i];
579 if (check_vic_exist(hdev, vic, i))
580 continue;
zhou.hana8e91612024-04-28 14:56:45 +0000581 prefer_vic = hdmitx21_get_prefer_vic(hdev, vic);
582 /* if mode_prefer_vic is support by RX, try 16x9 first */
583 if (prefer_vic != vic) {
584 printf("%s:prefer vic:%d exist, ignore [%d].\n", __func__, prefer_vic, vic);
585 continue;
586 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800587 timing = hdmitx21_gettiming_from_vic(vic);
588 if (timing && vic < HDMITX_VESA_OFFSET && !is_vic_over_limited_1080p(vic))
589 printf(" %s\n", timing->sname ? timing->sname : timing->name);
590 }
xiang.wu114497ab2024-02-21 14:57:05 +0800591 printf("420_cap\n");
592 for (i = 0; i < Y420_VIC_MAX_NUM; i++) {
593 vic = rxcap->y420_vic[i];
594 printf("420vic:%d\n", vic);
595 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800596}
597
598static void vesa_cap_show(struct hdmitx_dev *hdev)
599{
600}
601
602static void dc_cap_show(struct hdmitx_dev *hdev)
603{
604 enum hdmi_vic vic = HDMI_0_UNKNOWN;
605 struct rx_cap *prxcap = &hdev->RXCap;
606 const struct dv_info *dv = &hdev->RXCap.dv_info;
607
608 printf("dc_cap\n");
609 if (prxcap->dc_36bit_420)
610 printf("420,12bit\n");
611 if (prxcap->dc_30bit_420) {
612 printf("420,10bit\n");
613 printf("420,8bit\n");
614 } else {
615 vic = hdmitx_edid_get_VIC(hdev, "2160p60hz420", 0);
616 if (vic != HDMI_0_UNKNOWN) {
617 printf("420,8bit\n");
618 goto next444;
619 }
620 vic = hdmitx_edid_get_VIC(hdev, "2160p50hz420", 0);
621 if (vic != HDMI_0_UNKNOWN) {
622 printf("420,8bit\n");
623 goto next444;
624 }
625 vic = hdmitx_edid_get_VIC(hdev, "smpte60hz420", 0);
626 if (vic != HDMI_0_UNKNOWN) {
627 printf("420,8bit\n");
628 goto next444;
629 }
630 vic = hdmitx_edid_get_VIC(hdev, "smpte50hz420", 0);
631 if (vic != HDMI_0_UNKNOWN) {
632 printf("420,8bit\n");
633 goto next444;
634 }
635 }
636next444:
637 if (prxcap->native_Mode & (1 << 5)) {
638 if (prxcap->dc_y444) {
639 if (prxcap->dc_36bit || dv->sup_10b_12b_444 == 0x2)
640 printf("444,12bit\n");
641 if (prxcap->dc_30bit || dv->sup_10b_12b_444 == 0x1)
642 printf("444,10bit\n");
643 }
644 printf("444,8bit\n");
645 }
646 /* y422, not check dc */
647 if (prxcap->native_Mode & (1 << 4)) {
648 printf("422,12bit\n");
649 printf("422,10bit\n");
650 printf("422,8bit\n");
651 }
652
653 if (prxcap->dc_36bit || dv->sup_10b_12b_444 == 0x2)
654 printf("rgb,12bit\n");
655 if (prxcap->dc_30bit || dv->sup_10b_12b_444 == 0x1)
656 printf("rgb,10bit\n");
657 printf("rgb,8bit\n");
658}
659
660static void aud_cap_show(struct hdmitx_dev *hdev)
661{
662}
663
664static void hdr_cap_show(struct hdmitx_dev *hdev)
665{
666 int hdr10plugsupported = 0;
667 struct hdr_info *hdr = &hdev->RXCap.hdr_info;
xiang.wu114497ab2024-02-21 14:57:05 +0800668 const struct hdr10_plus_info *hdr10p = &hdev->RXCap.hdr_info.hdr10plus_info;
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800669
670 printf("\nhdr_cap\n");
671 if (hdr10p->ieeeoui == HDR10_PLUS_IEEE_OUI &&
672 hdr10p->application_version != 0xFF)
673 hdr10plugsupported = 1;
674 printf("HDR10Plus Supported: %d\n", hdr10plugsupported);
675 printf("HDR Static Metadata:\n");
676 printf(" Supported EOTF:\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800677 printf(" Traditional SDR: %d\n", !!(hdr->hdr_support & HDR_SUP_EOTF_SDR));
678 printf(" Traditional HDR: %d\n", !!(hdr->hdr_support & HDR_SUP_EOTF_HDR));
679 printf(" SMPTE ST 2084: %d\n", !!(hdr->hdr_support & HDR_SUP_EOTF_SMPTE_ST_2084));
680 printf(" Hybrid Log-Gamma: %d\n", !!(hdr->hdr_support & HDR_SUP_EOTF_HLG));
681 printf(" Supported SMD type1: %d\n", hdr->static_metadata_type1);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800682 printf(" Luminance Data\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800683 printf(" Max: %d\n", hdr->lumi_max);
684 printf(" Avg: %d\n", hdr->lumi_avg);
685 printf(" Min: %d\n\n", hdr->lumi_min);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800686 printf("HDR Dynamic Metadata:");
687}
688
689static void _dv_cap_show(const struct dv_info *dv)
690{
691 int i;
692
693 if (dv->ieeeoui != DV_IEEE_OUI || dv->block_flag != CORRECT) {
694 printf("The Rx don't support DolbyVision\n");
695 return;
696 }
697 printf("DolbyVision RX support list:\n");
698
699 if (dv->ver == 0) {
700 printf("VSVDB Version: V%d\n", dv->ver);
701 printf("2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
702 printf("Support mode:\n");
703 printf(" DV_RGB_444_8BIT\n");
704 if (dv->sup_yuv422_12bit)
705 printf(" DV_YCbCr_422_12BIT\n");
706 }
707 if (dv->ver == 1) {
708 printf("VSVDB Version: V%d(%d-byte)\n", dv->ver, dv->length + 1);
709 if (dv->length == 0xB) {
710 printf("2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
711 printf("Support mode:\n");
712 printf(" DV_RGB_444_8BIT\n");
713 if (dv->sup_yuv422_12bit)
714 printf(" DV_YCbCr_422_12BIT\n");
715 if (dv->low_latency == 0x01)
716 printf(" LL_YCbCr_422_12BIT\n");
717 }
718
719 if (dv->length == 0xE) {
720 printf("2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
721 printf("Support mode:\n");
722 printf(" DV_RGB_444_8BIT\n");
723 if (dv->sup_yuv422_12bit)
724 printf(" DV_YCbCr_422_12BIT\n");
725 }
726 }
727 if (dv->ver == 2) {
728 printf("VSVDB Version: V%d\n", dv->ver);
729 printf("2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
730 printf("Support mode:\n");
731 if (dv->Interface != 0x00 && dv->Interface != 0x01) {
732 printf(" DV_RGB_444_8BIT\n");
733 if (dv->sup_yuv422_12bit)
734 printf(" DV_YCbCr_422_12BIT\n");
735 }
736 printf(" LL_YCbCr_422_12BIT\n");
737 if (dv->Interface == 0x01 || dv->Interface == 0x03) {
738 if (dv->sup_10b_12b_444 == 0x1)
739 printf(" LL_RGB_444_10BIT\n");
740 if (dv->sup_10b_12b_444 == 0x2)
741 printf(" LL_RGB_444_12BIT\n");
742 }
743 }
744 printf("IEEEOUI: 0x%06x\n", dv->ieeeoui);
745 printf("VSVDB: ");
746 for (i = 0; i < (dv->length + 1); i++)
747 printf("%02x", dv->rawdata[i]);
748 printf("\n");
749}
750
751static void dv_cap_show(struct hdmitx_dev *hdev)
752{
753 const struct dv_info *dv = &hdev->RXCap.dv_info;
754
755 printf("dv_cap\n");
756 if (dv->ieeeoui != DV_IEEE_OUI) {
757 printf("The Rx don't support DolbyVision\n");
758 return;
759 }
760 _dv_cap_show(dv);
761}
762
763static void edid_cap_show(struct hdmitx_dev *hdev)
764{
765 int i;
766 struct rx_cap *prxcap = &hdev->RXCap;
767
xiang.wu114497ab2024-02-21 14:57:05 +0800768 printf("Rx EDID Parse:\n");
769 printf("Rx Manufacturer Name: %s\n", prxcap->IDManufacturerName);
770 printf("Rx Product Code: %02x%02x\n",
771 prxcap->IDProductCode[0], prxcap->IDProductCode[1]);
772 printf("Rx Serial Number: %02x%02x%02x%02x\n",
773 prxcap->IDSerialNumber[0],
774 prxcap->IDSerialNumber[1],
775 prxcap->IDSerialNumber[2],
776 prxcap->IDSerialNumber[3]);
777 printf("Rx Product Name: %s\n", prxcap->ReceiverProductName);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800778
xiang.wu114497ab2024-02-21 14:57:05 +0800779 printf("Manufacture Week: %d\n", prxcap->manufacture_week);
780 printf("Manufacture Year: %d\n", prxcap->manufacture_year + 1990);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800781
xiang.wu114497ab2024-02-21 14:57:05 +0800782 printf("Physical size(mm): %d x %d\n",
783 prxcap->physical_width, prxcap->physical_height);
784
785 printf("EDID Version: %d.%d\n",
786 prxcap->edid_version, prxcap->edid_revision);
787
788/* printf(
789 * "EDID block number: 0x%x\n", tx_comm->EDID_buf[0x7e]);
790 *
791 *
792 * printf(
793 * "Source Physical Address[a.b.c.d]: %x.%x.%x.%x\n",
794 * hdmitx_device->hdmi_info.vsdb_phy_addr.a,
795 * hdmitx_device->hdmi_info.vsdb_phy_addr.b,
796 * hdmitx_device->hdmi_info.vsdb_phy_addr.c,
797 * hdmitx_device->hdmi_info.vsdb_phy_addr.d);
798 */
799
800 // TODO native_vic2
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800801 printf("native Mode %x, VIC (native %d):\n",
xiang.wu114497ab2024-02-21 14:57:05 +0800802 prxcap->native_Mode, prxcap->native_vic);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800803
804 printf("ColorDeepSupport %x\n", prxcap->ColorDeepSupport);
805
xiang.wu114497ab2024-02-21 14:57:05 +0800806 for (i = 0; i < prxcap->VIC_count ; i++) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800807 printf("%d ", prxcap->VIC[i]);
xiang.wu114497ab2024-02-21 14:57:05 +0800808 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800809 printf("\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800810 printf("Audio {format, channel, freq, cce}\n");
811 for (i = 0; i < prxcap->AUD_count; i++) {
812 printf("{%d, %d, %x, %x}\n",
813 prxcap->RxAudioCap[i].audio_format_code,
814 prxcap->RxAudioCap[i].channel_num_max,
815 prxcap->RxAudioCap[i].freq_cc,
816 prxcap->RxAudioCap[i].cc3);
817 }
818 printf("Speaker Allocation: %x\n", prxcap->RxSpeakerAllocation);
819 printf("Vendor: 0x%x ( %s device)\n", prxcap->ieeeoui, (prxcap->ieeeoui) ? "HDMI" : "DVI");
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800820
821 printf("MaxTMDSClock1 %d MHz\n", prxcap->Max_TMDS_Clock1 * 5);
822
xiang.wu114497ab2024-02-21 14:57:05 +0800823 if (prxcap->hf_ieeeoui) {
824 printf("Vendor2: 0x%x\n",
825 prxcap->hf_ieeeoui);
826 printf("MaxTMDSClock2 %d MHz\n",
827 prxcap->Max_TMDS_Clock2 * 5);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800828 }
829
xiang.wu114497ab2024-02-21 14:57:05 +0800830 printf("MaxFRLRate: %d\n", prxcap->max_frl_rate);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800831
xiang.wu114497ab2024-02-21 14:57:05 +0800832 if (prxcap->allm)
833 printf("ALLM: %x\n", prxcap->allm);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800834
xiang.wu114497ab2024-02-21 14:57:05 +0800835 if (prxcap->cnc3)
836 printf("Game/CNC3: %x\n", prxcap->cnc3);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800837
xiang.wu114497ab2024-02-21 14:57:05 +0800838 printf("vLatency: ");
839 if (prxcap->vLatency == LATENCY_INVALID_UNKNOWN)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800840 printf(" Invalid/Unknown\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800841 else if (prxcap->vLatency == LATENCY_NOT_SUPPORT)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800842 printf(" UnSupported\n");
843 else
xiang.wu114497ab2024-02-21 14:57:05 +0800844 printf(" %d\n", prxcap->vLatency);
845
846 printf("aLatency: ");
847 if (prxcap->aLatency == LATENCY_INVALID_UNKNOWN)
848 printf(" Invalid/Unknown\n");
849 else if (prxcap->aLatency == LATENCY_NOT_SUPPORT)
850 printf(" UnSupported\n");
851 else
852 printf(" %d\n", prxcap->aLatency);
853
854 printf("i_vLatency: ");
855 if (prxcap->i_vLatency == LATENCY_INVALID_UNKNOWN)
856 printf(" Invalid/Unknown\n");
857 else if (prxcap->i_vLatency == LATENCY_NOT_SUPPORT)
858 printf(" UnSupported\n");
859 else
860 printf(" %d\n", prxcap->i_vLatency);
861
862 printf("i_aLatency: ");
863 if (prxcap->i_aLatency == LATENCY_INVALID_UNKNOWN)
864 printf(" Invalid/Unknown\n");
865 else if (prxcap->i_aLatency == LATENCY_NOT_SUPPORT)
866 printf(" UnSupported\n");
867 else
868 printf(" %d\n", prxcap->i_aLatency);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800869
870 if (prxcap->colorimetry_data)
871 printf("ColorMetry: 0x%x\n", prxcap->colorimetry_data);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800872
xiang.wu114497ab2024-02-21 14:57:05 +0800873 printf("SCDC: %x\n", prxcap->scdc_present);
874
875 printf("RR_Cap: %x\n",
876 prxcap->scdc_rr_capable);
877 printf("LTE_340M_Scramble: %x\n",
878 prxcap->lte_340mcsc_scramble);
879 /* dsc capability */
880 printf("dsc_10bpc: %d\n",
881 prxcap->dsc_10bpc);
882 printf("dsc_12bpc: %d\n",
883 prxcap->dsc_12bpc);
884 printf("dsc_16bpc: %d\n",
885 prxcap->dsc_16bpc);
886 printf("dsc_all_bpp: %d\n",
887 prxcap->dsc_all_bpp);
888 printf("dsc_native_420: %d\n",
889 prxcap->dsc_native_420);
890 printf("dsc_1p2: %d\n",
891 prxcap->dsc_1p2);
892 printf("dsc_max_slices: 0x%x(%d slices)\n",
893 prxcap->dsc_max_slices, dsc_max_slices_num[prxcap->dsc_max_slices]);
894 printf("dsc_max_frl_rate: 0x%x\n",
895 prxcap->dsc_max_frl_rate);
896 printf("dsc_total_chunk_bytes: 0x%x\n",
897 prxcap->dsc_total_chunk_bytes);
898 if (prxcap->dv_info.ieeeoui == DOVI_IEEEOUI)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800899 printf(" DolbyVision%d", prxcap->dv_info.ver);
xiang.wu114497ab2024-02-21 14:57:05 +0800900
901 if (prxcap->hdr_info2.hdr_support)
902 printf(" HDR/%d",
903 prxcap->hdr_info2.hdr_support);
904 if (prxcap->hdr_info.sbtm_info.sbtm_support)
905 printf(" SBTM");
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800906 if (prxcap->dc_y444 || prxcap->dc_30bit || prxcap->dc_30bit_420)
907 printf(" DeepColor");
908 printf("\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800909 printf("additional_vsif_num: %d\n", prxcap->additional_vsif_num);
910 printf("ifdb_present: %d\n", prxcap->ifdb_present);
911 /* for checkvalue which maybe used by application to adjust
912 * whether edid is changed
913 */
914 printf("checkvalue: %s\n", prxcap->hdmichecksum);
915
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800916}
917
918static int do_info(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
919{
920 struct hdmitx_dev *hdev = get_hdmitx21_device();
921 struct hdmi_format_para *para;
922
923 if (!hdev) {
924 pr_info("null hdmitx dev\n");
925 return CMD_RET_FAILURE;
926 }
927 if (!hdev->para) {
928 printf("null hdmitx para\n");
929 return CMD_RET_FAILURE;
930 }
931
932 para = hdev->para;
933 printf("current mode %s vic %d\n", para->timing.name, hdev->vic);
934 printf("cd%d cs%d cr%d\n", para->cd, para->cs, para->cr);
935 printf("enc_idx %d\n", hdev->enc_idx);
936 printf("frac_rate: %d\n", hdev->frac_rate_policy);
937 printf("Rx EDID info\n");
938 dump_full_edid(hdev->rawedid);
939 disp_cap_show(hdev);
940 vesa_cap_show(hdev);
941 aud_cap_show(hdev);
942 hdr_cap_show(hdev);
943 dv_cap_show(hdev);
944 dc_cap_show(hdev);
945 edid_cap_show(hdev);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800946 printf("dsc policy: %d, enable: %d\n", hdev->dsc_policy, hdev->dsc_en);
947 printf("frl_rate: %d\n", hdev->frl_rate);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800948 return 1;
949}
950
951static int xtochar(int num, char *checksum)
952{
953 struct hdmitx_dev *hdev = get_hdmitx21_device();
954
955 if (((hdev->rawedid[num] >> 4) & 0xf) <= 9)
956 checksum[0] = ((hdev->rawedid[num] >> 4) & 0xf) + '0';
957 else
958 checksum[0] = ((hdev->rawedid[num] >> 4) & 0xf) - 10 + 'a';
959
960 if ((hdev->rawedid[num] & 0xf) <= 9)
961 checksum[1] = (hdev->rawedid[num] & 0xf) + '0';
962 else
963 checksum[1] = (hdev->rawedid[num] & 0xf) - 10 + 'a';
964
965 return 0;
966}
967
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800968/* hdr_priority definition:
969 * strategy1: bit[3:0]
970 * 0: original cap
971 * 1: disable dolby vision cap
972 * 2: disable dolby vision and hdr/hlg cap
973 * strategy2:
974 * bit4: 1: disable dv 0:enable dv
975 * bit5: 1: disable hdr10/hdr10+ 0: enable hdr10/hdr10+
976 * bit6: 1: disable hlg 0: enable hlg
977 * bit28-bit31 choose strategy: bit[31:28]
978 * 0: strategy1
979 * 1: strategy2
980 */
981
982/* for uboot, there is no need to dynamically change the hdr_priority as
983 * kernel. So below functions only implement the disable_xxx_info() function,
984 * and leave the enable_xxx_info as blank
985 */
986
987/* dv_info */
988static void enable_dv_info(struct dv_info *des, const struct dv_info *src)
989{
990 if (!des || !src)
991 return;
992}
993
994static void disable_dv_info(struct dv_info *des)
995{
996 if (!des)
997 return;
998
999 memset(des, 0, sizeof(*des));
1000}
1001
1002/* hdr10 */
1003static void enable_hdr10_info(struct hdr_info *des, const struct hdr_info *src)
1004{
1005 if (!des || !src)
1006 return;
1007}
1008
1009static void disable_hdr10_info(struct hdr_info *des)
1010{
1011 if (!des)
1012 return;
1013
xiang.wu114497ab2024-02-21 14:57:05 +08001014 des->hdr_support = des->hdr_support & 0xB;
1015 des->static_metadata_type1 = 0;
1016 des->lumi_max = 0;
1017 des->lumi_avg = 0;
1018 des->lumi_min = 0;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001019}
1020
1021/* hdr10plus */
1022static void enable_hdr10p_info(struct hdr10_plus_info *des, const struct hdr10_plus_info *src)
1023{
1024 if (!des || !src)
1025 return;
1026}
1027
1028static void disable_hdr10p_info(struct hdr10_plus_info *des)
1029{
1030 if (!des)
1031 return;
1032
1033 memset(des, 0, sizeof(*des));
1034}
1035
1036/* hlg */
1037static void enable_hlg_info(struct hdr_info *des, const struct hdr_info *src)
1038{
1039 if (!des || !src)
1040 return;
1041}
1042
1043static void disable_hlg_info(struct hdr_info *des)
1044{
1045 if (!des)
1046 return;
1047
xiang.wu114497ab2024-02-21 14:57:05 +08001048 des->hdr_support = des->hdr_support & 0x7;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001049}
1050
1051static void enable_all_hdr_info(struct rx_cap *prxcap)
1052{
1053 if (!prxcap)
1054 return;
1055}
1056
1057static void update_hdr_strategy1(struct rx_cap *prxcap, u32 strategy)
1058{
1059 if (!prxcap)
1060 return;
1061
1062 switch (strategy) {
1063 case 0:
1064 enable_all_hdr_info(prxcap);
1065 break;
1066 case 1:
1067 disable_dv_info(&prxcap->dv_info);
1068 break;
1069 case 2:
1070 disable_dv_info(&prxcap->dv_info);
1071 disable_hdr10_info(&prxcap->hdr_info);
xiang.wu114497ab2024-02-21 14:57:05 +08001072 disable_hdr10p_info(&prxcap->hdr_info.hdr10plus_info);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001073 disable_hlg_info(&prxcap->hdr_info);
1074 break;
1075 default:
1076 break;
1077 }
1078}
1079
1080static void update_hdr_strategy2(struct rx_cap *prxcap, u32 strategy)
1081{
1082 if (!prxcap)
1083 return;
1084
1085 /* bit4: 1 disable dv 0 enable dv */
1086 if (strategy & BIT(4))
1087 disable_dv_info(&prxcap->dv_info);
1088 else
1089 enable_dv_info(&prxcap->dv_info, NULL);
1090 /* bit5: 1 disable hdr10/hdr10+ 0 enable hdr10/hdr10+ */
1091 if (strategy & BIT(5)) {
1092 disable_hdr10_info(&prxcap->hdr_info);
xiang.wu114497ab2024-02-21 14:57:05 +08001093 disable_hdr10p_info(&prxcap->hdr_info.hdr10plus_info);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001094 } else {
1095 enable_hdr10_info(&prxcap->hdr_info, NULL);
xiang.wu114497ab2024-02-21 14:57:05 +08001096 enable_hdr10p_info(&prxcap->hdr_info.hdr10plus_info, NULL);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001097 }
1098 /* bit6: 1 disable hlg 0 enable hlg */
1099 if (strategy & BIT(6))
1100 disable_hlg_info(&prxcap->hdr_info);
1101 else
1102 enable_hlg_info(&prxcap->hdr_info, NULL);
1103}
1104
1105static int hdmitx_set_hdr_priority(struct rx_cap *prxcap, u32 hdr_priority)
1106{
1107 u32 choose = 0;
1108 u32 strategy = 0;
1109
1110 if (!prxcap)
1111 return -1;
1112
1113 printf("%s, set hdr_prio: %u\n", __func__, hdr_priority);
1114 /* choose strategy: bit[31:28] */
1115 choose = (hdr_priority >> 28) & 0xf;
1116 switch (choose) {
1117 case 0:
1118 strategy = hdr_priority & 0xf;
1119 update_hdr_strategy1(prxcap, strategy);
1120 break;
1121 case 1:
1122 strategy = hdr_priority & 0xf0;
1123 update_hdr_strategy2(prxcap, strategy);
1124 break;
1125 default:
1126 break;
1127 }
1128 return 0;
1129}
1130
xiang.wu100ee50f2024-05-21 19:39:45 +08001131void hdmitx_update_dv_strategy_info(struct dv_info *dv)
1132{
1133 if (dv->ver == 0) {
1134 if (dv->length == 0x19)
1135 dv->support_DV_RGB_444_8BIT = 1;
1136 }
1137
1138 if (dv->ver == 1) {
1139 if (dv->length == 0x0B) {
1140 dv->support_DV_RGB_444_8BIT = 1;
1141 if (dv->low_latency == 0x01)
1142 dv->support_LL_YCbCr_422_12BIT = 1;
1143 } else if (dv->length == 0x0E) {
1144 dv->support_DV_RGB_444_8BIT = 1;
1145 }
1146 }
1147
1148 if (dv->ver == 2) {
1149 if (dv->length >= 0x0B) {
1150 if (dv->Interface != 0x00 && dv->Interface != 0x01)
1151 dv->support_DV_RGB_444_8BIT = 1;
1152 dv->support_LL_YCbCr_422_12BIT = 1;
1153 if (dv->Interface == 0x01 || dv->Interface == 0x03) {
1154 if (dv->sup_10b_12b_444 == 0x1)
1155 dv->support_LL_RGB_444_10BIT = 1;
1156 if (dv->sup_10b_12b_444 == 0x2)
1157 dv->support_LL_RGB_444_12BIT = 1;
1158 }
1159 }
1160 }
1161}
1162
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001163static void get_parse_edid_data(struct hdmitx_dev *hdev)
1164{
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001165 int hdr_priority = get_hdr_strategy_priority();
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001166
1167 hdev->hwop.read_edid(hdev->rawedid);
1168
ruofei.zhao4a2ec0c2023-10-31 19:24:41 +08001169 /* dump edid raw data */
1170 dump_full_edid(hdev->rawedid);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001171
1172 /* parse edid data */
xiang.wu114497ab2024-02-21 14:57:05 +08001173 hdmitx_edid_parse(&hdev->RXCap, hdev->rawedid);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001174
xiang.wu100ee50f2024-05-21 19:39:45 +08001175 /* Update the member variables used by the dv running strategy */
1176 hdmitx_update_dv_strategy_info(&hdev->RXCap.dv_info);
1177 hdmitx_update_dv_strategy_info(&hdev->RXCap.dv_info2);
1178
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001179 if (hdr_priority == -1)
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001180 return;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001181 hdmitx_set_hdr_priority(&hdev->RXCap, hdr_priority);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001182}
1183
1184/* policy process: to find the output mode/attr/dv_type */
1185void scene_process(struct hdmitx_dev *hdev,
1186 struct scene_output_info *scene_output_info)
1187{
1188 struct input_hdmi_data hdmidata;
hang cheng517b28d2024-04-24 21:20:38 +08001189 int dv_support = 0;
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001190
1191 if (!hdev || !scene_output_info)
1192 return;
1193 /* 1.read dolby vision mode from prop(maybe need to env) */
1194 memset(&hdmidata, 0, sizeof(struct input_hdmi_data));
1195 get_hdmi_data(hdev, &hdmidata);
1196
1197 /* 2. dolby vision scene process */
1198 /* only for tv support dv and box enable dv */
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001199 if (is_dv_preference(hdev)) {
hang cheng517b28d2024-04-24 21:20:38 +08001200 dv_support = dolbyvision_scene_process(&hdmidata, scene_output_info);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001201 } else if (is_dolby_enabled()) {
1202 /* for enable dolby vision core when
1203 * first boot connecting non dv tv
1204 * NOTE: let systemcontrol to enable DV core
1205 */
1206 /* scene_output_info->final_dv_type = DOLBY_VISION_ENABLE; */
1207 } else {
1208 /* for UI disable dolby vision core and boot keep the status
1209 * NOTE: TBD if need to disable DV here
1210 */
1211 /* scene_output_info->final_dv_type = DOLBY_VISION_DISABLE; */
1212 }
hang cheng517b28d2024-04-24 21:20:38 +08001213 /* 3.hdr/sdr scene process */
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001214 /* decide final display mode and deepcolor */
hang cheng517b28d2024-04-24 21:20:38 +08001215 if (is_dv_preference(hdev) && dv_support == 0) {
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001216 /* do nothing
1217 * already done above, just sync with sysctrl
1218 */
hang cheng517b28d2024-04-24 21:20:38 +08001219 } else if (is_hdr_preference(hdev) || dv_support != 0) {
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001220 hdr_scene_process(&hdmidata, scene_output_info);
1221 } else {
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001222 sdr_scene_process(&hdmidata, scene_output_info);
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001223 }
1224 /* not find outputmode and use default mode */
1225 if (strlen(scene_output_info->final_displaymode) == 0)
1226 strcpy(scene_output_info->final_displaymode, DEFAULT_HDMI_MODE);
1227 /* not find color space and use default mode */
1228 if (!strstr(scene_output_info->final_deepcolor, "bit"))
1229 strcpy(scene_output_info->final_deepcolor, DEFAULT_COLOR_FORMAT);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001230}
1231
1232static int do_get_parse_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1233{
1234 struct hdmitx_dev *hdev = get_hdmitx21_device();
1235 unsigned char *edid = hdev->rawedid;
1236 unsigned char *store_checkvalue;
1237
xiang.wu114497ab2024-02-21 14:57:05 +08001238 memset(edid, 0, EDID_BLK_SIZE * EDID_MAX_BLOCK);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001239 unsigned int i;
1240 unsigned int checkvalue[4];
1241 unsigned int checkvalue1;
1242 unsigned int checkvalue2;
1243 char checksum[11];
1244 unsigned char def_cksum[] = {'0', 'x', '0', '0', '0', '0', '0', '0', '0', '0', '\0'};
1245 char *hdmimode;
1246 char *colorattribute;
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001247 int user_dv_mode;
1248 char *last_output_mode;
1249 char *last_colorattribute;
1250 int last_dv_status;
1251 bool over_write = false;
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001252 char dv_type[2] = {0};
1253 struct scene_output_info scene_output_info;
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001254 struct hdmi_format_para *para = NULL;
1255 bool mode_support = false;
1256 /* hdmi_mode / colorattribute may be null or "none".
1257 * if either is null or "none", it means user not
1258 * selected manually, and need to select the best
1259 * mode or colorattribute by policy
1260 */
1261 bool no_manual_output = false;
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001262
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001263 if (!hdev->hpd_state) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001264 printf("HDMI HPD low, no need parse EDID\n");
1265 return 1;
1266 }
1267 memset(&scene_output_info, 0, sizeof(struct scene_output_info));
1268
1269 get_parse_edid_data(hdev);
1270
1271 /* check if the tv has changed or anything wrong */
1272 store_checkvalue = (unsigned char *)env_get("hdmichecksum");
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001273 /* get user selected output mode/color */
1274 colorattribute = env_get("user_colorattribute");
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001275 hdmimode = env_get("hdmimode");
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001276 user_dv_mode = get_ubootenv_dv_type();
1277
1278 last_output_mode = env_get("outputmode");
1279 last_colorattribute = env_get("colorattribute");
1280 last_dv_status = get_ubootenv_dv_status();
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001281 if (!store_checkvalue)
1282 store_checkvalue = def_cksum;
1283
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001284 printf("read hdmichecksum: %s, user hdmimode: %s, colorattribute: %s, dv_type: %d\n",
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001285 store_checkvalue, hdmimode ? hdmimode : "null",
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001286 colorattribute ? colorattribute : "null", user_dv_mode);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001287
1288 for (i = 0; i < 4; i++) {
1289 if (('0' <= store_checkvalue[i * 2 + 2]) && (store_checkvalue[i * 2 + 2] <= '9'))
1290 checkvalue1 = store_checkvalue[i * 2 + 2] - '0';
1291 else
1292 checkvalue1 = store_checkvalue[i * 2 + 2] - 'W';
1293 if (('0' <= store_checkvalue[i * 2 + 3]) && (store_checkvalue[i * 2 + 3] <= '9'))
1294 checkvalue2 = store_checkvalue[i * 2 + 3] - '0';
1295 else
1296 checkvalue2 = store_checkvalue[i * 2 + 3] - 'W';
1297 checkvalue[i] = checkvalue1 * 16 + checkvalue2;
1298 }
1299
1300 if (checkvalue[0] != hdev->rawedid[0x7f] ||
1301 checkvalue[1] != hdev->rawedid[0xff] ||
1302 checkvalue[2] != hdev->rawedid[0x17f] ||
1303 checkvalue[3] != hdev->rawedid[0x1ff]) {
1304 hdev->RXCap.edid_changed = 1;
1305
1306 checksum[0] = '0';
1307 checksum[1] = 'x';
1308 for (i = 0; i < 4; i++)
1309 xtochar(0x80 * i + 0x7f, &checksum[2 * i + 2]);
1310 checksum[10] = '\0';
xiang.wu114497ab2024-02-21 14:57:05 +08001311 memcpy(hdev->RXCap.hdmichecksum, checksum, 10);
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001312 printf("TV has changed, now crc: %s\n", checksum);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001313 } else {
xiang.wu114497ab2024-02-21 14:57:05 +08001314 memcpy(hdev->RXCap.hdmichecksum, store_checkvalue, 10);
1315 printf("TV is same, checksum: %s\n", hdev->RXCap.hdmichecksum);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001316 }
1317
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001318 /* check user have selected both mode/color or not */
1319 if (!hdmimode || !strcmp(hdmimode, "none") ||
1320 !colorattribute || !strcmp(colorattribute, "none"))
1321 no_manual_output = true;
1322 else
1323 no_manual_output = false;
1324
1325 if (!no_manual_output) {
1326 /* check current user selected mode + color support or not */
1327 para = hdmitx21_get_fmtpara(hdmimode, colorattribute);
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001328 if (hdmitx_edid_check_valid_mode(hdev, para)) {
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001329 mode_support = true;
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001330 } else {
1331 printf("saved output mode not supported!\n");
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001332 mode_support = false;
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001333 }
1334
1335 /* if user selected mode/color/dv type which saved in ubootenv of
1336 * hdmimode/user_colorattribute/user_prefer_dv_type are different
1337 * with last actual output mode/color/dv type which saved in
1338 * ubootenv of outputmode/colorattribute/dolby_status, then it means
1339 * that the user selected format is over-writen by policy(for example:
1340 * firstly user has selected HDR priority to HDR, and select color
1341 * to rgb,12bit(now the "user_colorattribute" env will be "rgb,12bit"),
1342 * but then it selected HDR priority to DV, the actual output color
1343 * will be "444,8bit" or "422,12bit" according to dv type, and
1344 * the ubootenv "colorattribute" will be "444,8bit" or "422,12bit"),
1345 * then uboot should use the policy to select the output format,
1346 * otherwise, uboot use hdmimode/user_colorattribute/user_prefer_dv_type
1347 * env, while system use outputmode/colorattribute/dolby_status env,
1348 * there will be always a mode change during bootup
1349 */
1350 if (mode_support) {
1351 /* note that for T7 multi-display, it may store panel in
1352 * "outputmode" env, and will always run uboot policy
1353 */
1354 if (!last_output_mode || strcmp(hdmimode, last_output_mode))
1355 over_write = true;
1356 else if (!last_colorattribute ||
1357 strcmp(colorattribute, last_colorattribute))
1358 over_write = true;
1359 else if (user_dv_mode != last_dv_status)
1360 over_write = true;
1361 else
1362 over_write = false;
1363
1364 if (over_write)
1365 printf("last output_mode:%s, colorattribute:%s, dolby_status:%d\n",
1366 last_output_mode ? last_output_mode : "null",
1367 last_colorattribute ? last_colorattribute : "null",
1368 last_dv_status);
1369 }
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001370 }
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001371 /* 4 cases need to decide output by uboot mode select policy:
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001372 * 1.TV changed
1373 * 2.either hdmimode or colorattribute is NULL or "none",
1374 * which means that user have not selected mode or colorattribute,
1375 * and need to select the auto best mode or best colorattribute.
1376 * 3.user selected mode not supportted by uboot (probably
1377 * means mode select policy or edid parse between sysctrl and
1378 * uboot have some gap), then need to find proper output mode
1379 * with uboot policy.
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001380 * 4.user selected mode is over writen by system policy
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001381 */
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001382 if (hdev->RXCap.edid_changed || no_manual_output || !mode_support || over_write) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001383 /* find proper mode if EDID changed */
1384 scene_process(hdev, &scene_output_info);
xiang.wu114497ab2024-02-21 14:57:05 +08001385 env_set("hdmichecksum", hdev->RXCap.hdmichecksum);
1386 if (hdmitx_edid_check_data_valid(0, hdev->rawedid)) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001387 /* SWPL-34712: if EDID parsing error case, not save env,
1388 * only output default mode(480p,RGB,8bit). after
1389 * EDID read OK, systemcontrol will recover the hdmi
1390 * mode from env, to avoid keep the default hdmi output
1391 */
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001392 memcpy(sel_hdmimode, scene_output_info.final_displaymode,
1393 sizeof(scene_output_info.final_displaymode));
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001394 if (is_hdmi_mode(env_get("outputmode"))) {
1395 env_set("outputmode",
1396 scene_output_info.final_displaymode);
1397 } else if (is_hdmi_mode(env_get("outputmode2"))) {
1398 env_set("outputmode2",
1399 scene_output_info.final_displaymode);
1400 } else if (is_hdmi_mode(env_get("outputmode3"))) {
1401 env_set("outputmode3",
1402 scene_output_info.final_displaymode);
1403 }
1404 env_set("colorattribute",
1405 scene_output_info.final_deepcolor);
1406 /* if change from DV TV to HDR/SDR TV, don't change
1407 * DV status to disabled, as DV core need to be enabled.
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001408 * that's to say connect DV TV & output DV-> power down box ->
1409 * connect HDR/SDR TV -> power on box, the dolby_status
1410 * will keep the same as that when connect DV TV under follow sink.
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001411 */
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001412 if (scene_output_info.final_dv_type != get_ubootenv_dv_status() &&
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001413 scene_output_info.final_dv_type != DOLBY_VISION_DISABLE) {
1414 sprintf(dv_type, "%d", scene_output_info.final_dv_type);
1415 env_set("dolby_status", dv_type);
1416 /* according to the policy of systemcontrol,
1417 * if current DV mode is not supported by TV
1418 * EDID, DV type maybe changed to one witch
1419 * TV support, and need VPP/DV module to
1420 * update new DV output mode.
1421 */
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001422 printf("update dolby_status: %d\n",
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001423 scene_output_info.final_dv_type);
1424 }
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001425 } else {
1426 save_default_720p();
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001427 }
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001428 printf("update outputmode: %s\n", sel_hdmimode);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001429 printf("update colorattribute: %s\n", env_get("colorattribute"));
1430 printf("update hdmichecksum: %s\n", env_get("hdmichecksum"));
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001431 } else {
1432 memset(sel_hdmimode, 0, sizeof(sel_hdmimode));
1433 memcpy(sel_hdmimode, hdmimode, strlen(hdmimode));
1434 if (is_hdmi_mode(env_get("outputmode")))
1435 env_set("outputmode", hdmimode);
1436 else if (is_hdmi_mode(env_get("outputmode2")))
1437 env_set("outputmode2", hdmimode);
1438 else if (is_hdmi_mode(env_get("outputmode3")))
1439 env_set("outputmode3", hdmimode);
1440 env_set("colorattribute", colorattribute);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001441 }
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001442 env_set("save_outputmode", sel_hdmimode);
1443 /* ubootenv dolby_status is used for is_dv_preference() decision,
1444 * system_control save current dv output status in it.
1445 * it will be used by dv module later to decide DV output later.
1446 * if currently adaptive hdr, then we should set dolby_status to
1447 * 0, so that DV module won't enable DV.
1448 */
1449 if (get_hdr_policy() == 1)
1450 env_set("dolby_status", 0);
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001451 hdev->para = hdmitx21_get_fmtpara(sel_hdmimode, env_get("colorattribute"));
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001452 hdev->vic = hdev->para->timing.vic;
1453 hdmitx_mask_rx_info(hdev);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001454 hdmitx21_select_frl(hdev);
1455 return 0;
1456}
1457
1458static int do_dsc_policy(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1459{
1460 struct hdmitx_dev *hdev = get_hdmitx21_device();
1461
1462 if (argc < 1)
1463 return cmd_usage(cmdtp);
1464
1465 if (strcmp(argv[1], "0") == 0)
1466 hdev->dsc_policy = 0;
1467 else if (strcmp(argv[1], "1") == 0)
1468 hdev->dsc_policy = 1;
1469 else if (strcmp(argv[1], "2") == 0)
1470 hdev->dsc_policy = 2;
1471 else if (strcmp(argv[1], "3") == 0)
1472 hdev->dsc_policy = 3;
1473 else if (strcmp(argv[1], "4") == 0)
1474 hdev->dsc_policy = 4;
1475 else
1476 printf("note: please set dsc policy as 0~4\n");
1477 if (hdev->dsc_policy <= 4)
1478 printf("use dsc policy: %d\n", hdev->dsc_policy);
1479
1480 return CMD_RET_SUCCESS;
1481}
1482
1483static int do_manual_frl_rate(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1484{
1485 struct hdmitx_dev *hdev = get_hdmitx21_device();
1486 unsigned int temp = 0;
1487 char *ptr;
1488
1489 /* if rx don't support FRL, return */
1490 if (!hdev->RXCap.max_frl_rate) {
1491 printf("rx not support FRL\n");
1492 return 0;
1493 }
1494
1495 temp = strtoul(argv[1], &ptr, 16);
1496 /* forced FRL rate setting */
1497 if (temp <= 6) {
1498 hdev->manual_frl_rate = temp;
1499 pr_info("force set frl_rate as %d\n", hdev->manual_frl_rate);
1500 } else {
1501 pr_info("error: should set frl_rate in 0 ~ 6\n");
1502 }
1503 if (hdev->manual_frl_rate > hdev->RXCap.max_frl_rate)
1504 pr_info("warning: larger than rx max_frl_rate %d\n", hdev->RXCap.max_frl_rate);
1505 return 0;
1506}
1507
1508static int do_manual_dfm_type(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1509{
1510 struct hdmitx_dev *hdev = get_hdmitx21_device();
1511 unsigned int temp = 0;
1512 char *ptr;
1513
1514 temp = strtoul(argv[1], &ptr, 10);
1515 /* forced dfm_type setting */
1516 if (temp <= 2) {
1517 hdev->dfm_type = temp;
1518 pr_info("force set dfm_type as %d\n", hdev->dfm_type);
1519 } else {
1520 pr_info("error: should set frl_rate in 0 ~ 2\n");
1521 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001522 return 0;
1523}
1524
Wenjie Qiao77833902023-12-18 19:01:59 +08001525#ifdef CONFIG_EFUSE_OBJ_API
1526static int do_efuse_show(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1527{
1528 struct hdmitx_dev *hdev = get_hdmitx21_device();
1529
1530 get_hdmi_efuse(hdev);
1531 pr_info("FEAT_DISABLE_HDMI_60HZ = %d\n", hdev->efuse_dis_hdmi_4k60);
1532 pr_info("FEAT_DISABLE_OUTPUT_4K = %d\n", hdev->efuse_dis_output_4k);
1533 pr_info("FEAT_DISABLE_HDCP_TX_22 = %d\n", hdev->efuse_dis_hdcp_tx22);
1534 pr_info("FEAT_DISABLE_HDMI_TX_3D = %d\n", hdev->efuse_dis_hdmi_tx3d);
1535 pr_info("FEAT_DISABLE_HDMI = %d\n", hdev->efuse_dis_hdcp_tx14);
1536
1537 return 0;
1538}
1539#endif
1540
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001541static cmd_tbl_t cmd_hdmi_sub[] = {
1542 U_BOOT_CMD_MKENT(hpd, 1, 1, do_hpd_detect, "", ""),
1543 U_BOOT_CMD_MKENT(edid, 3, 1, do_edid, "", ""),
1544 U_BOOT_CMD_MKENT(rx_det, 1, 1, do_rx_det, "", ""),
1545 U_BOOT_CMD_MKENT(output, 3, 1, do_output, "", ""),
1546 U_BOOT_CMD_MKENT(clkmsr, 3, 1, do_clkmsr, "", ""),
1547 U_BOOT_CMD_MKENT(blank, 3, 1, do_blank, "", ""),
1548 U_BOOT_CMD_MKENT(off, 1, 1, do_off, "", ""),
1549 U_BOOT_CMD_MKENT(dump, 1, 1, do_dump, "", ""),
1550 U_BOOT_CMD_MKENT(info, 1, 1, do_info, "", ""),
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001551 U_BOOT_CMD_MKENT(reg, 3, 1, do_reg, "", ""),
1552 U_BOOT_CMD_MKENT(get_parse_edid, 1, 1, do_get_parse_edid, "", ""),
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001553 U_BOOT_CMD_MKENT(dsc_policy, 1, 1, do_dsc_policy, "", ""),
1554 U_BOOT_CMD_MKENT(frl_rate, 1, 1, do_manual_frl_rate, "", ""),
1555 U_BOOT_CMD_MKENT(dfm_type, 1, 1, do_manual_dfm_type, "", ""),
Wenjie Qiao77833902023-12-18 19:01:59 +08001556#ifdef CONFIG_EFUSE_OBJ_API
1557 U_BOOT_CMD_MKENT(efuse, 1, 1, do_efuse_show, "", ""),
1558#endif
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001559 U_BOOT_CMD_MKENT(pbist, 3, 1, do_pbist, "", ""),
1560 U_BOOT_CMD_MKENT(debug, 3, 1, do_debug, "", ""),
xiang.wu1492f3642024-01-08 14:06:40 +08001561 U_BOOT_CMD_MKENT(s7_clk_config, 3, 1, do_s7_clk_config, "", ""),
xiang.wu114497ab2024-02-21 14:57:05 +08001562 U_BOOT_CMD_MKENT(get_rterm, 3, 1, get_rterm, "", ""),
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001563};
1564
1565static int do_hdmitx(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1566{
1567 cmd_tbl_t *c;
1568
1569 if (argc < 2)
1570 return cmd_usage(cmdtp);
1571
1572 argc--;
1573 argv++;
1574
1575 c = find_cmd_tbl(argv[0], &cmd_hdmi_sub[0], ARRAY_SIZE(cmd_hdmi_sub));
1576
1577 if (c)
1578 return c->cmd(cmdtp, flag, argc, argv);
1579 else
1580 return cmd_usage(cmdtp);
1581}
1582
1583U_BOOT_CMD(hdmitx, CONFIG_SYS_MAXARGS, 0, do_hdmitx,
1584 "HDMITX sub-system",
1585 "hdmitx version:20200618\n"
1586 "hdmitx hpd\n"
1587 " Detect hdmi rx plug-in\n"
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001588 "hdmitx output [list | FORMAT | bist PATTERN]\n"
1589 " list: list support formats\n"
1590 " FORMAT can be 720p60/50hz, 1080i60/50hz, 1080p60hz, etc\n"
1591 " extend with 8bits/10bits, y444/y422/y420/rgb\n"
1592 " such as 2160p60hz,10bits,y420\n"
1593 " PATTERN: can be as: line, dot, off, or 1920(width)\n"
1594 "hdmitx blank [0|1]\n"
1595 " 1: output blank 0: output normal\n"
1596 "hdmitx clkmsr\n"
1597 " show hdmitx clocks\n"
1598 "hdmitx off\n"
1599 " Turn off hdmitx output\n"
1600 "hdmitx info\n"
1601 " current mode info\n"
1602 "hdmitx rx_det\n"
1603 " Auto detect if RX is FBC and set outputmode\n"
1604);
1605
1606struct hdr_info *hdmitx_get_rx_hdr_info(void)
1607{
1608 struct hdmitx_dev *hdev = get_hdmitx21_device();
1609
1610 return &hdev->RXCap.hdr_info;
1611}
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001612
1613static int do_list_dsc_mode(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1614{
1615#ifdef CONFIG_AML_DSC_ENC
1616 dsc_enc_cap_show();
1617#endif
1618 return 0;
1619}
1620
1621static int do_dsc_debug(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1622{
1623#ifdef CONFIG_AML_DSC_ENC
1624 dsc_debug(argc - 1, argv + 1);
1625#endif
1626 return 0;
1627}
1628
1629static cmd_tbl_t cmd_dsc_sub[] = {
1630 U_BOOT_CMD_MKENT(list_mode, 1, 1, do_list_dsc_mode, "", ""),
1631 U_BOOT_CMD_MKENT(dbg, 20, 1, do_dsc_debug, "", ""),
1632};
1633
1634static int do_dsc_enc(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1635{
1636 cmd_tbl_t *c;
1637
1638 if (argc < 2)
1639 return cmd_usage(cmdtp);
1640
1641 argc--;
1642 argv++;
1643
1644 c = find_cmd_tbl(argv[0], &cmd_dsc_sub[0], ARRAY_SIZE(cmd_dsc_sub));
1645
1646 if (c)
1647 return c->cmd(cmdtp, flag, argc, argv);
1648 else
1649 return cmd_usage(cmdtp);
1650}
1651
1652U_BOOT_CMD(dsc, CONFIG_SYS_MAXARGS, 0, do_dsc_enc,
1653 "dsc cmd",
1654 "dsc help function\n"
1655 "dsc dbg state\n"
1656 " dump dsc status\n"
1657 "dsc dbg dump_reg\n"
1658 " dump dsc registers and venc registers\n"
1659 "dsc dbg read addr\n"
1660 " read dsc asic register\n"
1661 "dsc dbg write addr value\n"
1662 " write dsc asic register\n"
1663 "dsc dbg rst_dsc\n"
1664 " reset dsc enc\n"
1665 "dsc list_mode\n"
1666 " show supported dsc encode mode list\n"
1667);
1668