blob: 12ef85e85c29fd1e0e8ba6a9d05e87ec3eb8c3bc [file] [log] [blame]
Mark Brown2159ad932012-10-11 11:54:02 +09001/*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
Richard Fitzgerald605391d2018-08-08 17:13:39 +010013#include <linux/ctype.h>
Mark Brown2159ad932012-10-11 11:54:02 +090014#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/firmware.h>
Mark Browncf17c832013-01-30 14:37:23 +080019#include <linux/list.h>
Mark Brown2159ad932012-10-11 11:54:02 +090020#include <linux/pm.h>
21#include <linux/pm_runtime.h>
22#include <linux/regmap.h>
Mark Brown973838a2012-11-28 17:20:32 +000023#include <linux/regulator/consumer.h>
Mark Brown2159ad932012-10-11 11:54:02 +090024#include <linux/slab.h>
Charles Keepaxcdcd7f72014-11-14 15:40:45 +000025#include <linux/vmalloc.h>
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +010026#include <linux/workqueue.h>
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +010027#include <linux/debugfs.h>
Mark Brown2159ad932012-10-11 11:54:02 +090028#include <sound/core.h>
29#include <sound/pcm.h>
30#include <sound/pcm_params.h>
31#include <sound/soc.h>
32#include <sound/jack.h>
33#include <sound/initval.h>
34#include <sound/tlv.h>
35
Mark Brown2159ad932012-10-11 11:54:02 +090036#include "wm_adsp.h"
37
38#define adsp_crit(_dsp, fmt, ...) \
Richard Fitzgerald605391d2018-08-08 17:13:39 +010039 dev_crit(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
Mark Brown2159ad932012-10-11 11:54:02 +090040#define adsp_err(_dsp, fmt, ...) \
Richard Fitzgerald605391d2018-08-08 17:13:39 +010041 dev_err(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
Mark Brown2159ad932012-10-11 11:54:02 +090042#define adsp_warn(_dsp, fmt, ...) \
Richard Fitzgerald605391d2018-08-08 17:13:39 +010043 dev_warn(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
Mark Brown2159ad932012-10-11 11:54:02 +090044#define adsp_info(_dsp, fmt, ...) \
Richard Fitzgerald605391d2018-08-08 17:13:39 +010045 dev_info(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
Mark Brown2159ad932012-10-11 11:54:02 +090046#define adsp_dbg(_dsp, fmt, ...) \
Richard Fitzgerald605391d2018-08-08 17:13:39 +010047 dev_dbg(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
Mark Brown2159ad932012-10-11 11:54:02 +090048
49#define ADSP1_CONTROL_1 0x00
50#define ADSP1_CONTROL_2 0x02
51#define ADSP1_CONTROL_3 0x03
52#define ADSP1_CONTROL_4 0x04
53#define ADSP1_CONTROL_5 0x06
54#define ADSP1_CONTROL_6 0x07
55#define ADSP1_CONTROL_7 0x08
56#define ADSP1_CONTROL_8 0x09
57#define ADSP1_CONTROL_9 0x0A
58#define ADSP1_CONTROL_10 0x0B
59#define ADSP1_CONTROL_11 0x0C
60#define ADSP1_CONTROL_12 0x0D
61#define ADSP1_CONTROL_13 0x0F
62#define ADSP1_CONTROL_14 0x10
63#define ADSP1_CONTROL_15 0x11
64#define ADSP1_CONTROL_16 0x12
65#define ADSP1_CONTROL_17 0x13
66#define ADSP1_CONTROL_18 0x14
67#define ADSP1_CONTROL_19 0x16
68#define ADSP1_CONTROL_20 0x17
69#define ADSP1_CONTROL_21 0x18
70#define ADSP1_CONTROL_22 0x1A
71#define ADSP1_CONTROL_23 0x1B
72#define ADSP1_CONTROL_24 0x1C
73#define ADSP1_CONTROL_25 0x1E
74#define ADSP1_CONTROL_26 0x20
75#define ADSP1_CONTROL_27 0x21
76#define ADSP1_CONTROL_28 0x22
77#define ADSP1_CONTROL_29 0x23
78#define ADSP1_CONTROL_30 0x24
79#define ADSP1_CONTROL_31 0x26
80
81/*
82 * ADSP1 Control 19
83 */
84#define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
85#define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
86#define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
87
88
89/*
90 * ADSP1 Control 30
91 */
92#define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
93#define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
94#define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
95#define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
96#define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
97#define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
98#define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
99#define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
100#define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
101#define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
102#define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
103#define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
104#define ADSP1_START 0x0001 /* DSP1_START */
105#define ADSP1_START_MASK 0x0001 /* DSP1_START */
106#define ADSP1_START_SHIFT 0 /* DSP1_START */
107#define ADSP1_START_WIDTH 1 /* DSP1_START */
108
Chris Rattray94e205b2013-01-18 08:43:09 +0000109/*
110 * ADSP1 Control 31
111 */
112#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
113#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
114#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
115
Richard Fitzgeralde1ea1872017-04-05 11:07:59 +0100116#define ADSP2_CONTROL 0x0
117#define ADSP2_CLOCKING 0x1
118#define ADSP2V2_CLOCKING 0x2
119#define ADSP2_STATUS1 0x4
120#define ADSP2_WDMA_CONFIG_1 0x30
121#define ADSP2_WDMA_CONFIG_2 0x31
122#define ADSP2V2_WDMA_CONFIG_2 0x32
123#define ADSP2_RDMA_CONFIG_1 0x34
Mark Brown2159ad932012-10-11 11:54:02 +0900124
Richard Fitzgeralde1ea1872017-04-05 11:07:59 +0100125#define ADSP2_SCRATCH0 0x40
126#define ADSP2_SCRATCH1 0x41
127#define ADSP2_SCRATCH2 0x42
128#define ADSP2_SCRATCH3 0x43
129
130#define ADSP2V2_SCRATCH0_1 0x40
131#define ADSP2V2_SCRATCH2_3 0x42
Richard Fitzgerald10337b02015-05-29 10:23:07 +0100132
Mark Brown2159ad932012-10-11 11:54:02 +0900133/*
134 * ADSP2 Control
135 */
136
137#define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
138#define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
139#define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
140#define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
141#define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
142#define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
143#define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
144#define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
145#define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
146#define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
147#define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
148#define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
149#define ADSP2_START 0x0001 /* DSP1_START */
150#define ADSP2_START_MASK 0x0001 /* DSP1_START */
151#define ADSP2_START_SHIFT 0 /* DSP1_START */
152#define ADSP2_START_WIDTH 1 /* DSP1_START */
153
154/*
Mark Brown973838a2012-11-28 17:20:32 +0000155 * ADSP2 clocking
156 */
157#define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
158#define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
159#define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
160
161/*
Richard Fitzgeralde1ea1872017-04-05 11:07:59 +0100162 * ADSP2V2 clocking
163 */
164#define ADSP2V2_CLK_SEL_MASK 0x70000 /* CLK_SEL_ENA */
165#define ADSP2V2_CLK_SEL_SHIFT 16 /* CLK_SEL_ENA */
166#define ADSP2V2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
167
168#define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */
169#define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */
170#define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */
171
172/*
Mark Brown2159ad932012-10-11 11:54:02 +0900173 * ADSP2 Status 1
174 */
175#define ADSP2_RAM_RDY 0x0001
176#define ADSP2_RAM_RDY_MASK 0x0001
177#define ADSP2_RAM_RDY_SHIFT 0
178#define ADSP2_RAM_RDY_WIDTH 1
179
Mayuresh Kulkarni51a2c942017-04-05 11:08:00 +0100180/*
181 * ADSP2 Lock support
182 */
183#define ADSP2_LOCK_CODE_0 0x5555
184#define ADSP2_LOCK_CODE_1 0xAAAA
185
186#define ADSP2_WATCHDOG 0x0A
187#define ADSP2_BUS_ERR_ADDR 0x52
188#define ADSP2_REGION_LOCK_STATUS 0x64
189#define ADSP2_LOCK_REGION_1_LOCK_REGION_0 0x66
190#define ADSP2_LOCK_REGION_3_LOCK_REGION_2 0x68
191#define ADSP2_LOCK_REGION_5_LOCK_REGION_4 0x6A
192#define ADSP2_LOCK_REGION_7_LOCK_REGION_6 0x6C
193#define ADSP2_LOCK_REGION_9_LOCK_REGION_8 0x6E
194#define ADSP2_LOCK_REGION_CTRL 0x7A
195#define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x7C
196
197#define ADSP2_REGION_LOCK_ERR_MASK 0x8000
198#define ADSP2_SLAVE_ERR_MASK 0x4000
199#define ADSP2_WDT_TIMEOUT_STS_MASK 0x2000
200#define ADSP2_CTRL_ERR_PAUSE_ENA 0x0002
201#define ADSP2_CTRL_ERR_EINT 0x0001
202
203#define ADSP2_BUS_ERR_ADDR_MASK 0x00FFFFFF
204#define ADSP2_XMEM_ERR_ADDR_MASK 0x0000FFFF
205#define ADSP2_PMEM_ERR_ADDR_MASK 0x7FFF0000
206#define ADSP2_PMEM_ERR_ADDR_SHIFT 16
207#define ADSP2_WDT_ENA_MASK 0xFFFFFFFD
208
209#define ADSP2_LOCK_REGION_SHIFT 16
210
Charles Keepax9ee78752016-05-02 13:57:36 +0100211#define ADSP_MAX_STD_CTRL_SIZE 512
212
Richard Fitzgeraldf4f0c4c2016-11-09 17:14:17 +0000213#define WM_ADSP_ACKED_CTL_TIMEOUT_MS 100
214#define WM_ADSP_ACKED_CTL_N_QUICKPOLLS 10
Richard Fitzgeralda23ebba2016-11-09 17:14:18 +0000215#define WM_ADSP_ACKED_CTL_MIN_VALUE 0
216#define WM_ADSP_ACKED_CTL_MAX_VALUE 0xFFFFFF
Richard Fitzgeraldf4f0c4c2016-11-09 17:14:17 +0000217
218/*
219 * Event control messages
220 */
221#define WM_ADSP_FW_EVENT_SHUTDOWN 0x000001
222
Mark Browncf17c832013-01-30 14:37:23 +0800223struct wm_adsp_buf {
224 struct list_head list;
225 void *buf;
226};
227
228static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
229 struct list_head *list)
230{
231 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
232
233 if (buf == NULL)
234 return NULL;
235
Charles Keepaxcdcd7f72014-11-14 15:40:45 +0000236 buf->buf = vmalloc(len);
Mark Browncf17c832013-01-30 14:37:23 +0800237 if (!buf->buf) {
Richard Fitzgerald4d41c742016-12-09 09:57:41 +0000238 kfree(buf);
Mark Browncf17c832013-01-30 14:37:23 +0800239 return NULL;
240 }
Charles Keepaxcdcd7f72014-11-14 15:40:45 +0000241 memcpy(buf->buf, src, len);
Mark Browncf17c832013-01-30 14:37:23 +0800242
243 if (list)
244 list_add_tail(&buf->list, list);
245
246 return buf;
247}
248
249static void wm_adsp_buf_free(struct list_head *list)
250{
251 while (!list_empty(list)) {
252 struct wm_adsp_buf *buf = list_first_entry(list,
253 struct wm_adsp_buf,
254 list);
255 list_del(&buf->list);
Charles Keepaxcdcd7f72014-11-14 15:40:45 +0000256 vfree(buf->buf);
Mark Browncf17c832013-01-30 14:37:23 +0800257 kfree(buf);
258 }
259}
260
Charles Keepax04d13002015-11-26 14:01:52 +0000261#define WM_ADSP_FW_MBC_VSS 0
262#define WM_ADSP_FW_HIFI 1
263#define WM_ADSP_FW_TX 2
264#define WM_ADSP_FW_TX_SPK 3
265#define WM_ADSP_FW_RX 4
266#define WM_ADSP_FW_RX_ANC 5
267#define WM_ADSP_FW_CTRL 6
268#define WM_ADSP_FW_ASR 7
269#define WM_ADSP_FW_TRACE 8
270#define WM_ADSP_FW_SPK_PROT 9
271#define WM_ADSP_FW_MISC 10
Mark Brown1023dbd2013-01-11 22:58:28 +0000272
Charles Keepax04d13002015-11-26 14:01:52 +0000273#define WM_ADSP_NUM_FW 11
Mark Browndd84f922013-03-08 15:25:58 +0800274
Mark Brown1023dbd2013-01-11 22:58:28 +0000275static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
Charles Keepax04d13002015-11-26 14:01:52 +0000276 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
277 [WM_ADSP_FW_HIFI] = "MasterHiFi",
278 [WM_ADSP_FW_TX] = "Tx",
279 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
280 [WM_ADSP_FW_RX] = "Rx",
281 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
282 [WM_ADSP_FW_CTRL] = "Voice Ctrl",
283 [WM_ADSP_FW_ASR] = "ASR Assist",
284 [WM_ADSP_FW_TRACE] = "Dbg Trace",
285 [WM_ADSP_FW_SPK_PROT] = "Protection",
286 [WM_ADSP_FW_MISC] = "Misc",
Mark Brown1023dbd2013-01-11 22:58:28 +0000287};
288
Charles Keepax2cd19bd2015-12-15 11:29:46 +0000289struct wm_adsp_system_config_xm_hdr {
290 __be32 sys_enable;
291 __be32 fw_id;
292 __be32 fw_rev;
293 __be32 boot_status;
294 __be32 watchdog;
295 __be32 dma_buffer_size;
296 __be32 rdma[6];
297 __be32 wdma[8];
298 __be32 build_job_name[3];
299 __be32 build_job_number;
300};
301
302struct wm_adsp_alg_xm_struct {
303 __be32 magic;
304 __be32 smoothing;
305 __be32 threshold;
306 __be32 host_buf_ptr;
307 __be32 start_seq;
308 __be32 high_water_mark;
309 __be32 low_water_mark;
310 __be64 smoothed_power;
311};
312
313struct wm_adsp_buffer {
Richard Fitzgerald2a2aefa2018-10-19 13:25:15 +0100314 __be32 buf1_base; /* Base addr of first buffer area */
315 __be32 buf1_size; /* Size of buf1 area in DSP words */
316 __be32 buf2_base; /* Base addr of 2nd buffer area */
317 __be32 buf1_buf2_size; /* Size of buf1+buf2 in DSP words */
318 __be32 buf3_base; /* Base addr of buf3 area */
319 __be32 buf_total_size; /* Size of buf1+buf2+buf3 in DSP words */
Charles Keepax2cd19bd2015-12-15 11:29:46 +0000320 __be32 high_water_mark; /* Point at which IRQ is asserted */
321 __be32 irq_count; /* bits 1-31 count IRQ assertions */
322 __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */
323 __be32 next_write_index; /* word index of next write */
324 __be32 next_read_index; /* word index of next read */
325 __be32 error; /* error if any */
326 __be32 oldest_block_index; /* word index of oldest surviving */
327 __be32 requested_rewind; /* how many blocks rewind was done */
328 __be32 reserved_space; /* internal */
329 __be32 min_free; /* min free space since stream start */
330 __be32 blocks_written[2]; /* total blocks written (64 bit) */
331 __be32 words_written[2]; /* total words written (64 bit) */
332};
333
Charles Keepax721be3b2016-05-04 17:11:56 +0100334struct wm_adsp_compr;
335
Charles Keepax2cd19bd2015-12-15 11:29:46 +0000336struct wm_adsp_compr_buf {
337 struct wm_adsp *dsp;
Charles Keepax721be3b2016-05-04 17:11:56 +0100338 struct wm_adsp_compr *compr;
Charles Keepax2cd19bd2015-12-15 11:29:46 +0000339
340 struct wm_adsp_buffer_region *regions;
341 u32 host_buf_ptr;
Charles Keepax565ace42016-01-06 12:33:18 +0000342
343 u32 error;
344 u32 irq_count;
345 int read_index;
346 int avail;
Andrew Fordfb13f192019-02-19 17:31:56 +0000347 int host_buf_mem_type;
Charles Keepax2cd19bd2015-12-15 11:29:46 +0000348};
349
Charles Keepax406abc92015-12-15 11:29:45 +0000350struct wm_adsp_compr {
351 struct wm_adsp *dsp;
Charles Keepax95fe9592015-12-15 11:29:47 +0000352 struct wm_adsp_compr_buf *buf;
Charles Keepax406abc92015-12-15 11:29:45 +0000353
354 struct snd_compr_stream *stream;
355 struct snd_compressed_buffer size;
Charles Keepax565ace42016-01-06 12:33:18 +0000356
Charles Keepax83a40ce2016-01-06 12:33:19 +0000357 u32 *raw_buf;
Charles Keepax565ace42016-01-06 12:33:18 +0000358 unsigned int copied_total;
Charles Keepaxda2b3352016-02-02 16:41:36 +0000359
360 unsigned int sample_rate;
Charles Keepax406abc92015-12-15 11:29:45 +0000361};
362
363#define WM_ADSP_DATA_WORD_SIZE 3
364
365#define WM_ADSP_MIN_FRAGMENTS 1
366#define WM_ADSP_MAX_FRAGMENTS 256
367#define WM_ADSP_MIN_FRAGMENT_SIZE (64 * WM_ADSP_DATA_WORD_SIZE)
368#define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * WM_ADSP_DATA_WORD_SIZE)
369
Charles Keepax2cd19bd2015-12-15 11:29:46 +0000370#define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7
371
372#define HOST_BUFFER_FIELD(field) \
373 (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32))
374
375#define ALG_XM_FIELD(field) \
376 (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32))
377
378static int wm_adsp_buffer_init(struct wm_adsp *dsp);
379static int wm_adsp_buffer_free(struct wm_adsp *dsp);
380
381struct wm_adsp_buffer_region {
382 unsigned int offset;
383 unsigned int cumulative_size;
384 unsigned int mem_type;
385 unsigned int base_addr;
386};
387
388struct wm_adsp_buffer_region_def {
389 unsigned int mem_type;
390 unsigned int base_offset;
391 unsigned int size_offset;
392};
393
Charles Keepax3a9686c2016-02-01 15:22:34 +0000394static const struct wm_adsp_buffer_region_def default_regions[] = {
Charles Keepax2cd19bd2015-12-15 11:29:46 +0000395 {
396 .mem_type = WMFW_ADSP2_XM,
Richard Fitzgerald2a2aefa2018-10-19 13:25:15 +0100397 .base_offset = HOST_BUFFER_FIELD(buf1_base),
398 .size_offset = HOST_BUFFER_FIELD(buf1_size),
Charles Keepax2cd19bd2015-12-15 11:29:46 +0000399 },
400 {
401 .mem_type = WMFW_ADSP2_XM,
Richard Fitzgerald2a2aefa2018-10-19 13:25:15 +0100402 .base_offset = HOST_BUFFER_FIELD(buf2_base),
403 .size_offset = HOST_BUFFER_FIELD(buf1_buf2_size),
Charles Keepax2cd19bd2015-12-15 11:29:46 +0000404 },
405 {
406 .mem_type = WMFW_ADSP2_YM,
Richard Fitzgerald2a2aefa2018-10-19 13:25:15 +0100407 .base_offset = HOST_BUFFER_FIELD(buf3_base),
408 .size_offset = HOST_BUFFER_FIELD(buf_total_size),
Charles Keepax2cd19bd2015-12-15 11:29:46 +0000409 },
410};
411
Charles Keepax406abc92015-12-15 11:29:45 +0000412struct wm_adsp_fw_caps {
413 u32 id;
414 struct snd_codec_desc desc;
Charles Keepax2cd19bd2015-12-15 11:29:46 +0000415 int num_regions;
Charles Keepax3a9686c2016-02-01 15:22:34 +0000416 const struct wm_adsp_buffer_region_def *region_defs;
Charles Keepax406abc92015-12-15 11:29:45 +0000417};
418
Charles Keepaxe6d00f32016-01-21 17:52:58 +0000419static const struct wm_adsp_fw_caps ctrl_caps[] = {
Charles Keepax406abc92015-12-15 11:29:45 +0000420 {
421 .id = SND_AUDIOCODEC_BESPOKE,
422 .desc = {
Richard Fitzgerald3bbc2702018-07-19 11:50:38 +0100423 .max_ch = 8,
Charles Keepax406abc92015-12-15 11:29:45 +0000424 .sample_rates = { 16000 },
425 .num_sample_rates = 1,
426 .formats = SNDRV_PCM_FMTBIT_S16_LE,
427 },
Charles Keepaxe6d00f32016-01-21 17:52:58 +0000428 .num_regions = ARRAY_SIZE(default_regions),
429 .region_defs = default_regions,
Charles Keepax406abc92015-12-15 11:29:45 +0000430 },
431};
432
Charles Keepax7ce42832016-01-21 17:52:59 +0000433static const struct wm_adsp_fw_caps trace_caps[] = {
434 {
435 .id = SND_AUDIOCODEC_BESPOKE,
436 .desc = {
437 .max_ch = 8,
438 .sample_rates = {
439 4000, 8000, 11025, 12000, 16000, 22050,
440 24000, 32000, 44100, 48000, 64000, 88200,
441 96000, 176400, 192000
442 },
443 .num_sample_rates = 15,
444 .formats = SNDRV_PCM_FMTBIT_S16_LE,
445 },
446 .num_regions = ARRAY_SIZE(default_regions),
447 .region_defs = default_regions,
Charles Keepax406abc92015-12-15 11:29:45 +0000448 },
449};
450
451static const struct {
Mark Brown1023dbd2013-01-11 22:58:28 +0000452 const char *file;
Charles Keepax406abc92015-12-15 11:29:45 +0000453 int compr_direction;
454 int num_caps;
455 const struct wm_adsp_fw_caps *caps;
Charles Keepax20b7f7c2016-05-13 16:45:17 +0100456 bool voice_trigger;
Mark Brown1023dbd2013-01-11 22:58:28 +0000457} wm_adsp_fw[WM_ADSP_NUM_FW] = {
Charles Keepax04d13002015-11-26 14:01:52 +0000458 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
459 [WM_ADSP_FW_HIFI] = { .file = "hifi" },
460 [WM_ADSP_FW_TX] = { .file = "tx" },
461 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
462 [WM_ADSP_FW_RX] = { .file = "rx" },
463 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
Charles Keepax406abc92015-12-15 11:29:45 +0000464 [WM_ADSP_FW_CTRL] = {
465 .file = "ctrl",
466 .compr_direction = SND_COMPRESS_CAPTURE,
Charles Keepaxe6d00f32016-01-21 17:52:58 +0000467 .num_caps = ARRAY_SIZE(ctrl_caps),
468 .caps = ctrl_caps,
Charles Keepax20b7f7c2016-05-13 16:45:17 +0100469 .voice_trigger = true,
Charles Keepax406abc92015-12-15 11:29:45 +0000470 },
Charles Keepax04d13002015-11-26 14:01:52 +0000471 [WM_ADSP_FW_ASR] = { .file = "asr" },
Charles Keepax7ce42832016-01-21 17:52:59 +0000472 [WM_ADSP_FW_TRACE] = {
473 .file = "trace",
474 .compr_direction = SND_COMPRESS_CAPTURE,
475 .num_caps = ARRAY_SIZE(trace_caps),
476 .caps = trace_caps,
477 },
Charles Keepax04d13002015-11-26 14:01:52 +0000478 [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" },
479 [WM_ADSP_FW_MISC] = { .file = "misc" },
Mark Brown1023dbd2013-01-11 22:58:28 +0000480};
481
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100482struct wm_coeff_ctl_ops {
483 int (*xget)(struct snd_kcontrol *kcontrol,
484 struct snd_ctl_elem_value *ucontrol);
485 int (*xput)(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100487};
488
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100489struct wm_coeff_ctl {
490 const char *name;
Charles Keepax23237362015-04-13 13:28:02 +0100491 const char *fw_name;
Charles Keepax3809f002015-04-13 13:27:54 +0100492 struct wm_adsp_alg_region alg_region;
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100493 struct wm_coeff_ctl_ops ops;
Charles Keepax3809f002015-04-13 13:27:54 +0100494 struct wm_adsp *dsp;
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100495 unsigned int enabled:1;
496 struct list_head list;
497 void *cache;
Charles Keepax23237362015-04-13 13:28:02 +0100498 unsigned int offset;
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100499 size_t len;
Dimitris Papastamos0c2e3f32013-05-28 12:01:50 +0100500 unsigned int set:1;
Charles Keepax9ee78752016-05-02 13:57:36 +0100501 struct soc_bytes_ext bytes_ext;
Charles Keepax26c22a12015-04-20 13:52:45 +0100502 unsigned int flags;
Stuart Henderson8eb084d2016-11-09 17:14:16 +0000503 unsigned int type;
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100504};
505
Richard Fitzgerald9ce5e6e2016-11-09 17:14:15 +0000506static const char *wm_adsp_mem_region_name(unsigned int type)
507{
508 switch (type) {
509 case WMFW_ADSP1_PM:
510 return "PM";
511 case WMFW_ADSP1_DM:
512 return "DM";
513 case WMFW_ADSP2_XM:
514 return "XM";
515 case WMFW_ADSP2_YM:
516 return "YM";
517 case WMFW_ADSP1_ZM:
518 return "ZM";
519 default:
520 return NULL;
521 }
522}
523
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100524#ifdef CONFIG_DEBUG_FS
525static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s)
526{
527 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
528
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100529 kfree(dsp->wmfw_file_name);
530 dsp->wmfw_file_name = tmp;
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100531}
532
533static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s)
534{
535 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
536
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100537 kfree(dsp->bin_file_name);
538 dsp->bin_file_name = tmp;
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100539}
540
541static void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
542{
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100543 kfree(dsp->wmfw_file_name);
544 kfree(dsp->bin_file_name);
545 dsp->wmfw_file_name = NULL;
546 dsp->bin_file_name = NULL;
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100547}
548
549static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file,
550 char __user *user_buf,
551 size_t count, loff_t *ppos)
552{
553 struct wm_adsp *dsp = file->private_data;
554 ssize_t ret;
555
Charles Keepax078e7182015-12-08 16:08:26 +0000556 mutex_lock(&dsp->pwr_lock);
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100557
Charles Keepax28823eb2016-09-20 13:52:32 +0100558 if (!dsp->wmfw_file_name || !dsp->booted)
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100559 ret = 0;
560 else
561 ret = simple_read_from_buffer(user_buf, count, ppos,
562 dsp->wmfw_file_name,
563 strlen(dsp->wmfw_file_name));
564
Charles Keepax078e7182015-12-08 16:08:26 +0000565 mutex_unlock(&dsp->pwr_lock);
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100566 return ret;
567}
568
569static ssize_t wm_adsp_debugfs_bin_read(struct file *file,
570 char __user *user_buf,
571 size_t count, loff_t *ppos)
572{
573 struct wm_adsp *dsp = file->private_data;
574 ssize_t ret;
575
Charles Keepax078e7182015-12-08 16:08:26 +0000576 mutex_lock(&dsp->pwr_lock);
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100577
Charles Keepax28823eb2016-09-20 13:52:32 +0100578 if (!dsp->bin_file_name || !dsp->booted)
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100579 ret = 0;
580 else
581 ret = simple_read_from_buffer(user_buf, count, ppos,
582 dsp->bin_file_name,
583 strlen(dsp->bin_file_name));
584
Charles Keepax078e7182015-12-08 16:08:26 +0000585 mutex_unlock(&dsp->pwr_lock);
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100586 return ret;
587}
588
589static const struct {
590 const char *name;
591 const struct file_operations fops;
592} wm_adsp_debugfs_fops[] = {
593 {
594 .name = "wmfw_file_name",
595 .fops = {
596 .open = simple_open,
597 .read = wm_adsp_debugfs_wmfw_read,
598 },
599 },
600 {
601 .name = "bin_file_name",
602 .fops = {
603 .open = simple_open,
604 .read = wm_adsp_debugfs_bin_read,
605 },
606 },
607};
608
609static void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +0000610 struct snd_soc_component *component)
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100611{
612 struct dentry *root = NULL;
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100613 int i;
614
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +0000615 if (!component->debugfs_root) {
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100616 adsp_err(dsp, "No codec debugfs root\n");
617 goto err;
618 }
619
Richard Fitzgerald605391d2018-08-08 17:13:39 +0100620 root = debugfs_create_dir(dsp->name, component->debugfs_root);
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100621
622 if (!root)
623 goto err;
624
Joe Perches6a73cf42018-05-23 12:20:59 -0700625 if (!debugfs_create_bool("booted", 0444, root, &dsp->booted))
Charles Keepax28823eb2016-09-20 13:52:32 +0100626 goto err;
627
Joe Perches6a73cf42018-05-23 12:20:59 -0700628 if (!debugfs_create_bool("running", 0444, root, &dsp->running))
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100629 goto err;
630
Joe Perches6a73cf42018-05-23 12:20:59 -0700631 if (!debugfs_create_x32("fw_id", 0444, root, &dsp->fw_id))
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100632 goto err;
633
Joe Perches6a73cf42018-05-23 12:20:59 -0700634 if (!debugfs_create_x32("fw_version", 0444, root, &dsp->fw_id_version))
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100635 goto err;
636
637 for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) {
638 if (!debugfs_create_file(wm_adsp_debugfs_fops[i].name,
Joe Perches6a73cf42018-05-23 12:20:59 -0700639 0444, root, dsp,
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100640 &wm_adsp_debugfs_fops[i].fops))
641 goto err;
642 }
643
644 dsp->debugfs_root = root;
645 return;
646
647err:
648 debugfs_remove_recursive(root);
649 adsp_err(dsp, "Failed to create debugfs\n");
650}
651
652static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
653{
654 wm_adsp_debugfs_clear(dsp);
655 debugfs_remove_recursive(dsp->debugfs_root);
656}
657#else
658static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +0000659 struct snd_soc_component *component)
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +0100660{
661}
662
663static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
664{
665}
666
667static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp,
668 const char *s)
669{
670}
671
672static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp,
673 const char *s)
674{
675}
676
677static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
678{
679}
680#endif
681
Richard Fitzgerald0a047f02018-08-08 17:13:38 +0100682int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
683 struct snd_ctl_elem_value *ucontrol)
Mark Brown1023dbd2013-01-11 22:58:28 +0000684{
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +0000685 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
Mark Brown1023dbd2013-01-11 22:58:28 +0000686 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +0000687 struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
Mark Brown1023dbd2013-01-11 22:58:28 +0000688
Takashi Iwai15c66572016-02-29 18:01:18 +0100689 ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw;
Mark Brown1023dbd2013-01-11 22:58:28 +0000690
691 return 0;
692}
Richard Fitzgerald0a047f02018-08-08 17:13:38 +0100693EXPORT_SYMBOL_GPL(wm_adsp_fw_get);
Mark Brown1023dbd2013-01-11 22:58:28 +0000694
Richard Fitzgerald0a047f02018-08-08 17:13:38 +0100695int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
696 struct snd_ctl_elem_value *ucontrol)
Mark Brown1023dbd2013-01-11 22:58:28 +0000697{
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +0000698 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
Mark Brown1023dbd2013-01-11 22:58:28 +0000699 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +0000700 struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
Charles Keepaxd27c5e12015-12-08 16:08:28 +0000701 int ret = 0;
Mark Brown1023dbd2013-01-11 22:58:28 +0000702
Takashi Iwai15c66572016-02-29 18:01:18 +0100703 if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw)
Mark Brown1023dbd2013-01-11 22:58:28 +0000704 return 0;
705
Takashi Iwai15c66572016-02-29 18:01:18 +0100706 if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW)
Mark Brown1023dbd2013-01-11 22:58:28 +0000707 return -EINVAL;
708
Charles Keepaxd27c5e12015-12-08 16:08:28 +0000709 mutex_lock(&dsp[e->shift_l].pwr_lock);
710
Charles Keepax28823eb2016-09-20 13:52:32 +0100711 if (dsp[e->shift_l].booted || dsp[e->shift_l].compr)
Charles Keepaxd27c5e12015-12-08 16:08:28 +0000712 ret = -EBUSY;
713 else
Takashi Iwai15c66572016-02-29 18:01:18 +0100714 dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0];
Mark Brown1023dbd2013-01-11 22:58:28 +0000715
Charles Keepaxd27c5e12015-12-08 16:08:28 +0000716 mutex_unlock(&dsp[e->shift_l].pwr_lock);
Mark Brown1023dbd2013-01-11 22:58:28 +0000717
Charles Keepaxd27c5e12015-12-08 16:08:28 +0000718 return ret;
Mark Brown1023dbd2013-01-11 22:58:28 +0000719}
Richard Fitzgerald0a047f02018-08-08 17:13:38 +0100720EXPORT_SYMBOL_GPL(wm_adsp_fw_put);
Mark Brown1023dbd2013-01-11 22:58:28 +0000721
Richard Fitzgerald0a047f02018-08-08 17:13:38 +0100722const struct soc_enum wm_adsp_fw_enum[] = {
Mark Brown1023dbd2013-01-11 22:58:28 +0000723 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
724 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
725 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
726 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
Richard Fitzgeralde1ea1872017-04-05 11:07:59 +0100727 SOC_ENUM_SINGLE(0, 4, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
728 SOC_ENUM_SINGLE(0, 5, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
729 SOC_ENUM_SINGLE(0, 6, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
Mark Brown1023dbd2013-01-11 22:58:28 +0000730};
Richard Fitzgerald0a047f02018-08-08 17:13:38 +0100731EXPORT_SYMBOL_GPL(wm_adsp_fw_enum);
Mark Brown2159ad932012-10-11 11:54:02 +0900732
733static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
734 int type)
735{
736 int i;
737
738 for (i = 0; i < dsp->num_mems; i++)
739 if (dsp->mem[i].type == type)
740 return &dsp->mem[i];
741
742 return NULL;
743}
744
Charles Keepax3809f002015-04-13 13:27:54 +0100745static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
Mark Brown45b9ee72013-01-08 16:02:06 +0000746 unsigned int offset)
747{
Charles Keepax3809f002015-04-13 13:27:54 +0100748 if (WARN_ON(!mem))
Takashi Iwai6c452bd2013-11-05 18:40:00 +0100749 return offset;
Charles Keepax3809f002015-04-13 13:27:54 +0100750 switch (mem->type) {
Mark Brown45b9ee72013-01-08 16:02:06 +0000751 case WMFW_ADSP1_PM:
Charles Keepax3809f002015-04-13 13:27:54 +0100752 return mem->base + (offset * 3);
Mark Brown45b9ee72013-01-08 16:02:06 +0000753 case WMFW_ADSP1_DM:
Charles Keepax3809f002015-04-13 13:27:54 +0100754 return mem->base + (offset * 2);
Mark Brown45b9ee72013-01-08 16:02:06 +0000755 case WMFW_ADSP2_XM:
Charles Keepax3809f002015-04-13 13:27:54 +0100756 return mem->base + (offset * 2);
Mark Brown45b9ee72013-01-08 16:02:06 +0000757 case WMFW_ADSP2_YM:
Charles Keepax3809f002015-04-13 13:27:54 +0100758 return mem->base + (offset * 2);
Mark Brown45b9ee72013-01-08 16:02:06 +0000759 case WMFW_ADSP1_ZM:
Charles Keepax3809f002015-04-13 13:27:54 +0100760 return mem->base + (offset * 2);
Mark Brown45b9ee72013-01-08 16:02:06 +0000761 default:
Takashi Iwai6c452bd2013-11-05 18:40:00 +0100762 WARN(1, "Unknown memory region type");
Mark Brown45b9ee72013-01-08 16:02:06 +0000763 return offset;
764 }
765}
766
Richard Fitzgerald10337b02015-05-29 10:23:07 +0100767static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
768{
Richard Fitzgerald20e00db2018-11-12 13:36:38 +0000769 unsigned int scratch[4];
770 unsigned int addr = dsp->base + ADSP2_SCRATCH0;
771 unsigned int i;
Richard Fitzgerald10337b02015-05-29 10:23:07 +0100772 int ret;
773
Richard Fitzgerald20e00db2018-11-12 13:36:38 +0000774 for (i = 0; i < ARRAY_SIZE(scratch); ++i) {
775 ret = regmap_read(dsp->regmap, addr + i, &scratch[i]);
776 if (ret) {
777 adsp_err(dsp, "Failed to read SCRATCH%u: %d\n", i, ret);
778 return;
779 }
Richard Fitzgerald10337b02015-05-29 10:23:07 +0100780 }
781
782 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
Richard Fitzgerald20e00db2018-11-12 13:36:38 +0000783 scratch[0], scratch[1], scratch[2], scratch[3]);
Richard Fitzgerald10337b02015-05-29 10:23:07 +0100784}
785
Richard Fitzgeralde1ea1872017-04-05 11:07:59 +0100786static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp)
787{
Richard Fitzgerald20e00db2018-11-12 13:36:38 +0000788 unsigned int scratch[2];
Richard Fitzgeralde1ea1872017-04-05 11:07:59 +0100789 int ret;
790
Richard Fitzgerald20e00db2018-11-12 13:36:38 +0000791 ret = regmap_read(dsp->regmap, dsp->base + ADSP2V2_SCRATCH0_1,
792 &scratch[0]);
Richard Fitzgeralde1ea1872017-04-05 11:07:59 +0100793 if (ret) {
Richard Fitzgerald20e00db2018-11-12 13:36:38 +0000794 adsp_err(dsp, "Failed to read SCRATCH0_1: %d\n", ret);
Richard Fitzgeralde1ea1872017-04-05 11:07:59 +0100795 return;
796 }
797
Richard Fitzgerald20e00db2018-11-12 13:36:38 +0000798 ret = regmap_read(dsp->regmap, dsp->base + ADSP2V2_SCRATCH2_3,
799 &scratch[1]);
800 if (ret) {
801 adsp_err(dsp, "Failed to read SCRATCH2_3: %d\n", ret);
802 return;
803 }
Richard Fitzgeralde1ea1872017-04-05 11:07:59 +0100804
805 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
806 scratch[0] & 0xFFFF,
807 scratch[0] >> 16,
808 scratch[1] & 0xFFFF,
809 scratch[1] >> 16);
810}
811
Charles Keepax9ee78752016-05-02 13:57:36 +0100812static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext)
813{
814 return container_of(ext, struct wm_coeff_ctl, bytes_ext);
815}
816
Richard Fitzgeraldb396ebc2016-11-09 17:14:14 +0000817static int wm_coeff_base_reg(struct wm_coeff_ctl *ctl, unsigned int *reg)
818{
819 const struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
820 struct wm_adsp *dsp = ctl->dsp;
821 const struct wm_adsp_region *mem;
822
823 mem = wm_adsp_find_region(dsp, alg_region->type);
824 if (!mem) {
825 adsp_err(dsp, "No base for region %x\n",
826 alg_region->type);
827 return -EINVAL;
828 }
829
830 *reg = wm_adsp_region_to_reg(mem, ctl->alg_region.base + ctl->offset);
831
832 return 0;
833}
834
Charles Keepax7585a5b2015-12-08 16:08:25 +0000835static int wm_coeff_info(struct snd_kcontrol *kctl,
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100836 struct snd_ctl_elem_info *uinfo)
837{
Charles Keepax9ee78752016-05-02 13:57:36 +0100838 struct soc_bytes_ext *bytes_ext =
839 (struct soc_bytes_ext *)kctl->private_value;
840 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100841
Richard Fitzgeralda23ebba2016-11-09 17:14:18 +0000842 switch (ctl->type) {
843 case WMFW_CTL_TYPE_ACKED:
844 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
845 uinfo->value.integer.min = WM_ADSP_ACKED_CTL_MIN_VALUE;
846 uinfo->value.integer.max = WM_ADSP_ACKED_CTL_MAX_VALUE;
847 uinfo->value.integer.step = 1;
848 uinfo->count = 1;
849 break;
850 default:
851 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
852 uinfo->count = ctl->len;
853 break;
854 }
855
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100856 return 0;
857}
858
Richard Fitzgeraldf4f0c4c2016-11-09 17:14:17 +0000859static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl,
860 unsigned int event_id)
861{
862 struct wm_adsp *dsp = ctl->dsp;
863 u32 val = cpu_to_be32(event_id);
864 unsigned int reg;
865 int i, ret;
866
867 ret = wm_coeff_base_reg(ctl, &reg);
868 if (ret)
869 return ret;
870
871 adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n",
872 event_id, ctl->alg_region.alg,
873 wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset);
874
875 ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val));
876 if (ret) {
877 adsp_err(dsp, "Failed to write %x: %d\n", reg, ret);
878 return ret;
879 }
880
881 /*
882 * Poll for ack, we initially poll at ~1ms intervals for firmwares
883 * that respond quickly, then go to ~10ms polls. A firmware is unlikely
884 * to ack instantly so we do the first 1ms delay before reading the
885 * control to avoid a pointless bus transaction
886 */
887 for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) {
888 switch (i) {
889 case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS - 1:
890 usleep_range(1000, 2000);
891 i++;
892 break;
893 default:
894 usleep_range(10000, 20000);
895 i += 10;
896 break;
897 }
898
899 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
900 if (ret) {
901 adsp_err(dsp, "Failed to read %x: %d\n", reg, ret);
902 return ret;
903 }
904
905 if (val == 0) {
906 adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i);
907 return 0;
908 }
909 }
910
911 adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n",
912 reg, ctl->alg_region.alg,
913 wm_adsp_mem_region_name(ctl->alg_region.type),
914 ctl->offset);
915
916 return -ETIMEDOUT;
917}
918
Charles Keepaxc9f8dd72015-04-13 13:27:58 +0100919static int wm_coeff_write_control(struct wm_coeff_ctl *ctl,
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100920 const void *buf, size_t len)
921{
Charles Keepax3809f002015-04-13 13:27:54 +0100922 struct wm_adsp *dsp = ctl->dsp;
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100923 void *scratch;
924 int ret;
925 unsigned int reg;
926
Richard Fitzgeraldb396ebc2016-11-09 17:14:14 +0000927 ret = wm_coeff_base_reg(ctl, &reg);
928 if (ret)
929 return ret;
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100930
Charles Keepax4f8ea6d2016-02-19 14:44:44 +0000931 scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100932 if (!scratch)
933 return -ENOMEM;
934
Charles Keepax3809f002015-04-13 13:27:54 +0100935 ret = regmap_raw_write(dsp->regmap, reg, scratch,
Charles Keepax4f8ea6d2016-02-19 14:44:44 +0000936 len);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100937 if (ret) {
Charles Keepax3809f002015-04-13 13:27:54 +0100938 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
Charles Keepax4f8ea6d2016-02-19 14:44:44 +0000939 len, reg, ret);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100940 kfree(scratch);
941 return ret;
942 }
Charles Keepax4f8ea6d2016-02-19 14:44:44 +0000943 adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100944
945 kfree(scratch);
946
947 return 0;
948}
949
Charles Keepax7585a5b2015-12-08 16:08:25 +0000950static int wm_coeff_put(struct snd_kcontrol *kctl,
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100951 struct snd_ctl_elem_value *ucontrol)
952{
Charles Keepax9ee78752016-05-02 13:57:36 +0100953 struct soc_bytes_ext *bytes_ext =
954 (struct soc_bytes_ext *)kctl->private_value;
955 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100956 char *p = ucontrol->value.bytes.data;
Charles Keepax168d10e2015-12-08 16:08:27 +0000957 int ret = 0;
958
959 mutex_lock(&ctl->dsp->pwr_lock);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100960
Charles Keepax67430a32017-03-06 16:54:33 +0000961 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
962 ret = -EPERM;
963 else
964 memcpy(ctl->cache, p, ctl->len);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100965
Nikesh Oswal65d17a92015-02-16 15:25:48 +0000966 ctl->set = 1;
Charles Keepaxcef45772016-09-20 13:52:33 +0100967 if (ctl->enabled && ctl->dsp->running)
Charles Keepax168d10e2015-12-08 16:08:27 +0000968 ret = wm_coeff_write_control(ctl, p, ctl->len);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100969
Charles Keepax168d10e2015-12-08 16:08:27 +0000970 mutex_unlock(&ctl->dsp->pwr_lock);
971
972 return ret;
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +0100973}
974
Charles Keepax9ee78752016-05-02 13:57:36 +0100975static int wm_coeff_tlv_put(struct snd_kcontrol *kctl,
976 const unsigned int __user *bytes, unsigned int size)
977{
978 struct soc_bytes_ext *bytes_ext =
979 (struct soc_bytes_ext *)kctl->private_value;
980 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
981 int ret = 0;
982
983 mutex_lock(&ctl->dsp->pwr_lock);
984
985 if (copy_from_user(ctl->cache, bytes, size)) {
986 ret = -EFAULT;
987 } else {
988 ctl->set = 1;
Charles Keepaxcef45772016-09-20 13:52:33 +0100989 if (ctl->enabled && ctl->dsp->running)
Charles Keepax9ee78752016-05-02 13:57:36 +0100990 ret = wm_coeff_write_control(ctl, ctl->cache, size);
Charles Keepax67430a32017-03-06 16:54:33 +0000991 else if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
992 ret = -EPERM;
Charles Keepax9ee78752016-05-02 13:57:36 +0100993 }
994
995 mutex_unlock(&ctl->dsp->pwr_lock);
996
997 return ret;
998}
999
Richard Fitzgeralda23ebba2016-11-09 17:14:18 +00001000static int wm_coeff_put_acked(struct snd_kcontrol *kctl,
1001 struct snd_ctl_elem_value *ucontrol)
1002{
1003 struct soc_bytes_ext *bytes_ext =
1004 (struct soc_bytes_ext *)kctl->private_value;
1005 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1006 unsigned int val = ucontrol->value.integer.value[0];
1007 int ret;
1008
1009 if (val == 0)
1010 return 0; /* 0 means no event */
1011
1012 mutex_lock(&ctl->dsp->pwr_lock);
1013
Charles Keepax7b4af792017-03-06 16:54:34 +00001014 if (ctl->enabled && ctl->dsp->running)
Richard Fitzgeralda23ebba2016-11-09 17:14:18 +00001015 ret = wm_coeff_write_acked_control(ctl, val);
1016 else
1017 ret = -EPERM;
1018
1019 mutex_unlock(&ctl->dsp->pwr_lock);
1020
1021 return ret;
1022}
1023
Charles Keepaxc9f8dd72015-04-13 13:27:58 +01001024static int wm_coeff_read_control(struct wm_coeff_ctl *ctl,
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01001025 void *buf, size_t len)
1026{
Charles Keepax3809f002015-04-13 13:27:54 +01001027 struct wm_adsp *dsp = ctl->dsp;
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01001028 void *scratch;
1029 int ret;
1030 unsigned int reg;
1031
Richard Fitzgeraldb396ebc2016-11-09 17:14:14 +00001032 ret = wm_coeff_base_reg(ctl, &reg);
1033 if (ret)
1034 return ret;
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01001035
Charles Keepax4f8ea6d2016-02-19 14:44:44 +00001036 scratch = kmalloc(len, GFP_KERNEL | GFP_DMA);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01001037 if (!scratch)
1038 return -ENOMEM;
1039
Charles Keepax4f8ea6d2016-02-19 14:44:44 +00001040 ret = regmap_raw_read(dsp->regmap, reg, scratch, len);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01001041 if (ret) {
Charles Keepax3809f002015-04-13 13:27:54 +01001042 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
Charles Keepax5602a642016-03-10 10:46:07 +00001043 len, reg, ret);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01001044 kfree(scratch);
1045 return ret;
1046 }
Charles Keepax4f8ea6d2016-02-19 14:44:44 +00001047 adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01001048
Charles Keepax4f8ea6d2016-02-19 14:44:44 +00001049 memcpy(buf, scratch, len);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01001050 kfree(scratch);
1051
1052 return 0;
1053}
1054
Charles Keepax7585a5b2015-12-08 16:08:25 +00001055static int wm_coeff_get(struct snd_kcontrol *kctl,
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01001056 struct snd_ctl_elem_value *ucontrol)
1057{
Charles Keepax9ee78752016-05-02 13:57:36 +01001058 struct soc_bytes_ext *bytes_ext =
1059 (struct soc_bytes_ext *)kctl->private_value;
1060 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01001061 char *p = ucontrol->value.bytes.data;
Charles Keepax168d10e2015-12-08 16:08:27 +00001062 int ret = 0;
1063
1064 mutex_lock(&ctl->dsp->pwr_lock);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01001065
Charles Keepax26c22a12015-04-20 13:52:45 +01001066 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
Charles Keepaxcef45772016-09-20 13:52:33 +01001067 if (ctl->enabled && ctl->dsp->running)
Charles Keepax168d10e2015-12-08 16:08:27 +00001068 ret = wm_coeff_read_control(ctl, p, ctl->len);
Charles Keepax26c22a12015-04-20 13:52:45 +01001069 else
Charles Keepax168d10e2015-12-08 16:08:27 +00001070 ret = -EPERM;
1071 } else {
Charles Keepaxcef45772016-09-20 13:52:33 +01001072 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
Charles Keepaxbc1765d2015-12-17 10:05:59 +00001073 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
1074
Charles Keepax168d10e2015-12-08 16:08:27 +00001075 memcpy(p, ctl->cache, ctl->len);
Charles Keepax26c22a12015-04-20 13:52:45 +01001076 }
1077
Charles Keepax168d10e2015-12-08 16:08:27 +00001078 mutex_unlock(&ctl->dsp->pwr_lock);
Charles Keepax26c22a12015-04-20 13:52:45 +01001079
Charles Keepax168d10e2015-12-08 16:08:27 +00001080 return ret;
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01001081}
1082
Charles Keepax9ee78752016-05-02 13:57:36 +01001083static int wm_coeff_tlv_get(struct snd_kcontrol *kctl,
1084 unsigned int __user *bytes, unsigned int size)
1085{
1086 struct soc_bytes_ext *bytes_ext =
1087 (struct soc_bytes_ext *)kctl->private_value;
1088 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1089 int ret = 0;
1090
1091 mutex_lock(&ctl->dsp->pwr_lock);
1092
1093 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
Charles Keepaxcef45772016-09-20 13:52:33 +01001094 if (ctl->enabled && ctl->dsp->running)
Charles Keepax9ee78752016-05-02 13:57:36 +01001095 ret = wm_coeff_read_control(ctl, ctl->cache, size);
1096 else
1097 ret = -EPERM;
1098 } else {
Charles Keepaxcef45772016-09-20 13:52:33 +01001099 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
Charles Keepax9ee78752016-05-02 13:57:36 +01001100 ret = wm_coeff_read_control(ctl, ctl->cache, size);
1101 }
1102
1103 if (!ret && copy_to_user(bytes, ctl->cache, size))
1104 ret = -EFAULT;
1105
1106 mutex_unlock(&ctl->dsp->pwr_lock);
1107
1108 return ret;
1109}
1110
Richard Fitzgeralda23ebba2016-11-09 17:14:18 +00001111static int wm_coeff_get_acked(struct snd_kcontrol *kcontrol,
1112 struct snd_ctl_elem_value *ucontrol)
1113{
1114 /*
1115 * Although it's not useful to read an acked control, we must satisfy
1116 * user-side assumptions that all controls are readable and that a
1117 * write of the same value should be filtered out (it's valid to send
1118 * the same event number again to the firmware). We therefore return 0,
1119 * meaning "no event" so valid event numbers will always be a change
1120 */
1121 ucontrol->value.integer.value[0] = 0;
1122
1123 return 0;
1124}
1125
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01001126struct wmfw_ctl_work {
Charles Keepax3809f002015-04-13 13:27:54 +01001127 struct wm_adsp *dsp;
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01001128 struct wm_coeff_ctl *ctl;
1129 struct work_struct work;
1130};
1131
Charles Keepax9ee78752016-05-02 13:57:36 +01001132static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len)
1133{
1134 unsigned int out, rd, wr, vol;
1135
1136 if (len > ADSP_MAX_STD_CTRL_SIZE) {
1137 rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ;
1138 wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE;
1139 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1140
1141 out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK;
1142 } else {
1143 rd = SNDRV_CTL_ELEM_ACCESS_READ;
1144 wr = SNDRV_CTL_ELEM_ACCESS_WRITE;
1145 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1146
1147 out = 0;
1148 }
1149
1150 if (in) {
1151 if (in & WMFW_CTL_FLAG_READABLE)
1152 out |= rd;
1153 if (in & WMFW_CTL_FLAG_WRITEABLE)
1154 out |= wr;
1155 if (in & WMFW_CTL_FLAG_VOLATILE)
1156 out |= vol;
1157 } else {
1158 out |= rd | wr | vol;
1159 }
1160
1161 return out;
1162}
1163
Charles Keepax3809f002015-04-13 13:27:54 +01001164static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01001165{
1166 struct snd_kcontrol_new *kcontrol;
1167 int ret;
1168
Dimitris Papastamos92bb4c32013-08-01 11:11:28 +01001169 if (!ctl || !ctl->name)
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01001170 return -EINVAL;
1171
1172 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
1173 if (!kcontrol)
1174 return -ENOMEM;
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01001175
1176 kcontrol->name = ctl->name;
1177 kcontrol->info = wm_coeff_info;
Charles Keepax9ee78752016-05-02 13:57:36 +01001178 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1179 kcontrol->tlv.c = snd_soc_bytes_tlv_callback;
1180 kcontrol->private_value = (unsigned long)&ctl->bytes_ext;
Charles Keepax9ee78752016-05-02 13:57:36 +01001181 kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len);
Charles Keepax26c22a12015-04-20 13:52:45 +01001182
Richard Fitzgeralda23ebba2016-11-09 17:14:18 +00001183 switch (ctl->type) {
1184 case WMFW_CTL_TYPE_ACKED:
1185 kcontrol->get = wm_coeff_get_acked;
1186 kcontrol->put = wm_coeff_put_acked;
1187 break;
1188 default:
Richard Fitzgeraldd7789f52018-02-28 10:31:10 +00001189 if (kcontrol->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
1190 ctl->bytes_ext.max = ctl->len;
1191 ctl->bytes_ext.get = wm_coeff_tlv_get;
1192 ctl->bytes_ext.put = wm_coeff_tlv_put;
1193 } else {
1194 kcontrol->get = wm_coeff_get;
1195 kcontrol->put = wm_coeff_put;
1196 }
Richard Fitzgeralda23ebba2016-11-09 17:14:18 +00001197 break;
1198 }
1199
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +00001200 ret = snd_soc_add_component_controls(dsp->component, kcontrol, 1);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01001201 if (ret < 0)
1202 goto err_kcontrol;
1203
1204 kfree(kcontrol);
1205
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01001206 return 0;
1207
1208err_kcontrol:
1209 kfree(kcontrol);
1210 return ret;
1211}
1212
Charles Keepaxb21acc12015-04-13 13:28:01 +01001213static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
1214{
1215 struct wm_coeff_ctl *ctl;
1216 int ret;
1217
1218 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1219 if (!ctl->enabled || ctl->set)
1220 continue;
Charles Keepax26c22a12015-04-20 13:52:45 +01001221 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1222 continue;
1223
Richard Fitzgerald04ff40a2018-02-05 11:38:17 +00001224 /*
1225 * For readable controls populate the cache from the DSP memory.
1226 * For non-readable controls the cache was zero-filled when
1227 * created so we don't need to do anything.
1228 */
1229 if (!ctl->flags || (ctl->flags & WMFW_CTL_FLAG_READABLE)) {
1230 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
1231 if (ret < 0)
1232 return ret;
1233 }
Charles Keepaxb21acc12015-04-13 13:28:01 +01001234 }
1235
1236 return 0;
1237}
1238
1239static int wm_coeff_sync_controls(struct wm_adsp *dsp)
1240{
1241 struct wm_coeff_ctl *ctl;
1242 int ret;
1243
1244 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1245 if (!ctl->enabled)
1246 continue;
Charles Keepax26c22a12015-04-20 13:52:45 +01001247 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
Charles Keepax7d00cd92016-02-19 14:44:43 +00001248 ret = wm_coeff_write_control(ctl, ctl->cache, ctl->len);
Charles Keepaxb21acc12015-04-13 13:28:01 +01001249 if (ret < 0)
1250 return ret;
1251 }
1252 }
1253
1254 return 0;
1255}
1256
Richard Fitzgeraldf4f0c4c2016-11-09 17:14:17 +00001257static void wm_adsp_signal_event_controls(struct wm_adsp *dsp,
1258 unsigned int event)
1259{
1260 struct wm_coeff_ctl *ctl;
1261 int ret;
1262
1263 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1264 if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT)
1265 continue;
1266
Charles Keepax87aa6372016-11-21 18:00:02 +00001267 if (!ctl->enabled)
1268 continue;
1269
Richard Fitzgeraldf4f0c4c2016-11-09 17:14:17 +00001270 ret = wm_coeff_write_acked_control(ctl, event);
1271 if (ret)
1272 adsp_warn(dsp,
1273 "Failed to send 0x%x event to alg 0x%x (%d)\n",
1274 event, ctl->alg_region.alg, ret);
1275 }
1276}
1277
Charles Keepaxb21acc12015-04-13 13:28:01 +01001278static void wm_adsp_ctl_work(struct work_struct *work)
1279{
1280 struct wmfw_ctl_work *ctl_work = container_of(work,
1281 struct wmfw_ctl_work,
1282 work);
1283
1284 wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
1285 kfree(ctl_work);
1286}
1287
Richard Fitzgerald66225e92016-04-27 14:58:27 +01001288static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl)
1289{
1290 kfree(ctl->cache);
1291 kfree(ctl->name);
1292 kfree(ctl);
1293}
1294
Charles Keepaxb21acc12015-04-13 13:28:01 +01001295static int wm_adsp_create_control(struct wm_adsp *dsp,
1296 const struct wm_adsp_alg_region *alg_region,
Charles Keepax23237362015-04-13 13:28:02 +01001297 unsigned int offset, unsigned int len,
Charles Keepax26c22a12015-04-20 13:52:45 +01001298 const char *subname, unsigned int subname_len,
Stuart Henderson8eb084d2016-11-09 17:14:16 +00001299 unsigned int flags, unsigned int type)
Charles Keepaxb21acc12015-04-13 13:28:01 +01001300{
1301 struct wm_coeff_ctl *ctl;
1302 struct wmfw_ctl_work *ctl_work;
1303 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
Richard Fitzgerald9ce5e6e2016-11-09 17:14:15 +00001304 const char *region_name;
Charles Keepaxb21acc12015-04-13 13:28:01 +01001305 int ret;
1306
Richard Fitzgerald9ce5e6e2016-11-09 17:14:15 +00001307 region_name = wm_adsp_mem_region_name(alg_region->type);
1308 if (!region_name) {
Charles Keepax23237362015-04-13 13:28:02 +01001309 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
Charles Keepaxb21acc12015-04-13 13:28:01 +01001310 return -EINVAL;
1311 }
1312
Charles Keepaxcb5b57a2015-04-13 13:28:04 +01001313 switch (dsp->fw_ver) {
1314 case 0:
1315 case 1:
Richard Fitzgerald605391d2018-08-08 17:13:39 +01001316 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s %s %x",
1317 dsp->name, region_name, alg_region->alg);
Charles Keepaxcb5b57a2015-04-13 13:28:04 +01001318 break;
1319 default:
1320 ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
Richard Fitzgerald605391d2018-08-08 17:13:39 +01001321 "%s%c %.12s %x", dsp->name, *region_name,
Charles Keepaxcb5b57a2015-04-13 13:28:04 +01001322 wm_adsp_fw_text[dsp->fw], alg_region->alg);
1323
1324 /* Truncate the subname from the start if it is too long */
1325 if (subname) {
1326 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
1327 int skip = 0;
1328
Charles Keepaxb7ede5af2018-07-19 11:50:36 +01001329 if (dsp->component->name_prefix)
1330 avail -= strlen(dsp->component->name_prefix) + 1;
1331
Charles Keepaxcb5b57a2015-04-13 13:28:04 +01001332 if (subname_len > avail)
1333 skip = subname_len - avail;
1334
1335 snprintf(name + ret,
1336 SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, " %.*s",
1337 subname_len - skip, subname + skip);
1338 }
1339 break;
1340 }
Charles Keepaxb21acc12015-04-13 13:28:01 +01001341
Charles Keepax7585a5b2015-12-08 16:08:25 +00001342 list_for_each_entry(ctl, &dsp->ctl_list, list) {
Charles Keepaxb21acc12015-04-13 13:28:01 +01001343 if (!strcmp(ctl->name, name)) {
1344 if (!ctl->enabled)
1345 ctl->enabled = 1;
1346 return 0;
1347 }
1348 }
1349
1350 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
1351 if (!ctl)
1352 return -ENOMEM;
Charles Keepax23237362015-04-13 13:28:02 +01001353 ctl->fw_name = wm_adsp_fw_text[dsp->fw];
Charles Keepaxb21acc12015-04-13 13:28:01 +01001354 ctl->alg_region = *alg_region;
1355 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
1356 if (!ctl->name) {
1357 ret = -ENOMEM;
1358 goto err_ctl;
1359 }
1360 ctl->enabled = 1;
1361 ctl->set = 0;
1362 ctl->ops.xget = wm_coeff_get;
1363 ctl->ops.xput = wm_coeff_put;
1364 ctl->dsp = dsp;
1365
Charles Keepax26c22a12015-04-20 13:52:45 +01001366 ctl->flags = flags;
Stuart Henderson8eb084d2016-11-09 17:14:16 +00001367 ctl->type = type;
Charles Keepax23237362015-04-13 13:28:02 +01001368 ctl->offset = offset;
Charles Keepaxb21acc12015-04-13 13:28:01 +01001369 ctl->len = len;
1370 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
1371 if (!ctl->cache) {
1372 ret = -ENOMEM;
1373 goto err_ctl_name;
1374 }
1375
Charles Keepax23237362015-04-13 13:28:02 +01001376 list_add(&ctl->list, &dsp->ctl_list);
1377
Stuart Henderson8eb084d2016-11-09 17:14:16 +00001378 if (flags & WMFW_CTL_FLAG_SYS)
1379 return 0;
1380
Charles Keepaxb21acc12015-04-13 13:28:01 +01001381 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
1382 if (!ctl_work) {
1383 ret = -ENOMEM;
1384 goto err_ctl_cache;
1385 }
1386
1387 ctl_work->dsp = dsp;
1388 ctl_work->ctl = ctl;
1389 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
1390 schedule_work(&ctl_work->work);
1391
1392 return 0;
1393
1394err_ctl_cache:
1395 kfree(ctl->cache);
1396err_ctl_name:
1397 kfree(ctl->name);
1398err_ctl:
1399 kfree(ctl);
1400
1401 return ret;
1402}
1403
Charles Keepax23237362015-04-13 13:28:02 +01001404struct wm_coeff_parsed_alg {
1405 int id;
1406 const u8 *name;
1407 int name_len;
1408 int ncoeff;
1409};
1410
1411struct wm_coeff_parsed_coeff {
1412 int offset;
1413 int mem_type;
1414 const u8 *name;
1415 int name_len;
1416 int ctl_type;
1417 int flags;
1418 int len;
1419};
1420
Charles Keepaxcb5b57a2015-04-13 13:28:04 +01001421static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
1422{
1423 int length;
1424
1425 switch (bytes) {
1426 case 1:
1427 length = **pos;
1428 break;
1429 case 2:
Charles Keepax8299ee82015-04-20 13:52:44 +01001430 length = le16_to_cpu(*((__le16 *)*pos));
Charles Keepaxcb5b57a2015-04-13 13:28:04 +01001431 break;
1432 default:
1433 return 0;
1434 }
1435
1436 if (str)
1437 *str = *pos + bytes;
1438
1439 *pos += ((length + bytes) + 3) & ~0x03;
1440
1441 return length;
1442}
1443
1444static int wm_coeff_parse_int(int bytes, const u8 **pos)
1445{
1446 int val = 0;
1447
1448 switch (bytes) {
1449 case 2:
Charles Keepax8299ee82015-04-20 13:52:44 +01001450 val = le16_to_cpu(*((__le16 *)*pos));
Charles Keepaxcb5b57a2015-04-13 13:28:04 +01001451 break;
1452 case 4:
Charles Keepax8299ee82015-04-20 13:52:44 +01001453 val = le32_to_cpu(*((__le32 *)*pos));
Charles Keepaxcb5b57a2015-04-13 13:28:04 +01001454 break;
1455 default:
1456 break;
1457 }
1458
1459 *pos += bytes;
1460
1461 return val;
1462}
1463
Charles Keepax23237362015-04-13 13:28:02 +01001464static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
1465 struct wm_coeff_parsed_alg *blk)
1466{
1467 const struct wmfw_adsp_alg_data *raw;
1468
Charles Keepaxcb5b57a2015-04-13 13:28:04 +01001469 switch (dsp->fw_ver) {
1470 case 0:
1471 case 1:
1472 raw = (const struct wmfw_adsp_alg_data *)*data;
1473 *data = raw->data;
Charles Keepax23237362015-04-13 13:28:02 +01001474
Charles Keepaxcb5b57a2015-04-13 13:28:04 +01001475 blk->id = le32_to_cpu(raw->id);
1476 blk->name = raw->name;
1477 blk->name_len = strlen(raw->name);
1478 blk->ncoeff = le32_to_cpu(raw->ncoeff);
1479 break;
1480 default:
1481 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
1482 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
1483 &blk->name);
1484 wm_coeff_parse_string(sizeof(u16), data, NULL);
1485 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
1486 break;
1487 }
Charles Keepax23237362015-04-13 13:28:02 +01001488
1489 adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
1490 adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
1491 adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
1492}
1493
1494static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
1495 struct wm_coeff_parsed_coeff *blk)
1496{
1497 const struct wmfw_adsp_coeff_data *raw;
Charles Keepaxcb5b57a2015-04-13 13:28:04 +01001498 const u8 *tmp;
1499 int length;
Charles Keepax23237362015-04-13 13:28:02 +01001500
Charles Keepaxcb5b57a2015-04-13 13:28:04 +01001501 switch (dsp->fw_ver) {
1502 case 0:
1503 case 1:
1504 raw = (const struct wmfw_adsp_coeff_data *)*data;
1505 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
Charles Keepax23237362015-04-13 13:28:02 +01001506
Charles Keepaxcb5b57a2015-04-13 13:28:04 +01001507 blk->offset = le16_to_cpu(raw->hdr.offset);
1508 blk->mem_type = le16_to_cpu(raw->hdr.type);
1509 blk->name = raw->name;
1510 blk->name_len = strlen(raw->name);
1511 blk->ctl_type = le16_to_cpu(raw->ctl_type);
1512 blk->flags = le16_to_cpu(raw->flags);
1513 blk->len = le32_to_cpu(raw->len);
1514 break;
1515 default:
1516 tmp = *data;
1517 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
1518 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
1519 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
1520 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
1521 &blk->name);
1522 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
1523 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
1524 blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
1525 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
1526 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
1527
1528 *data = *data + sizeof(raw->hdr) + length;
1529 break;
1530 }
Charles Keepax23237362015-04-13 13:28:02 +01001531
1532 adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
1533 adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
1534 adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
1535 adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
1536 adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
1537 adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
1538}
1539
Richard Fitzgeraldf4f0c4c2016-11-09 17:14:17 +00001540static int wm_adsp_check_coeff_flags(struct wm_adsp *dsp,
1541 const struct wm_coeff_parsed_coeff *coeff_blk,
1542 unsigned int f_required,
1543 unsigned int f_illegal)
1544{
1545 if ((coeff_blk->flags & f_illegal) ||
1546 ((coeff_blk->flags & f_required) != f_required)) {
1547 adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n",
1548 coeff_blk->flags, coeff_blk->ctl_type);
1549 return -EINVAL;
1550 }
1551
1552 return 0;
1553}
1554
Charles Keepax23237362015-04-13 13:28:02 +01001555static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
1556 const struct wmfw_region *region)
1557{
1558 struct wm_adsp_alg_region alg_region = {};
1559 struct wm_coeff_parsed_alg alg_blk;
1560 struct wm_coeff_parsed_coeff coeff_blk;
1561 const u8 *data = region->data;
1562 int i, ret;
1563
1564 wm_coeff_parse_alg(dsp, &data, &alg_blk);
1565 for (i = 0; i < alg_blk.ncoeff; i++) {
1566 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
1567
1568 switch (coeff_blk.ctl_type) {
1569 case SNDRV_CTL_ELEM_TYPE_BYTES:
1570 break;
Richard Fitzgeralda23ebba2016-11-09 17:14:18 +00001571 case WMFW_CTL_TYPE_ACKED:
1572 if (coeff_blk.flags & WMFW_CTL_FLAG_SYS)
1573 continue; /* ignore */
1574
1575 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1576 WMFW_CTL_FLAG_VOLATILE |
1577 WMFW_CTL_FLAG_WRITEABLE |
1578 WMFW_CTL_FLAG_READABLE,
1579 0);
1580 if (ret)
1581 return -EINVAL;
1582 break;
Richard Fitzgeraldf4f0c4c2016-11-09 17:14:17 +00001583 case WMFW_CTL_TYPE_HOSTEVENT:
1584 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1585 WMFW_CTL_FLAG_SYS |
1586 WMFW_CTL_FLAG_VOLATILE |
1587 WMFW_CTL_FLAG_WRITEABLE |
1588 WMFW_CTL_FLAG_READABLE,
1589 0);
1590 if (ret)
1591 return -EINVAL;
1592 break;
Richard Fitzgeraldd52ed4b2018-07-19 11:50:39 +01001593 case WMFW_CTL_TYPE_HOST_BUFFER:
1594 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1595 WMFW_CTL_FLAG_SYS |
1596 WMFW_CTL_FLAG_VOLATILE |
1597 WMFW_CTL_FLAG_READABLE,
1598 0);
1599 if (ret)
1600 return -EINVAL;
1601 break;
Charles Keepax23237362015-04-13 13:28:02 +01001602 default:
1603 adsp_err(dsp, "Unknown control type: %d\n",
1604 coeff_blk.ctl_type);
1605 return -EINVAL;
1606 }
1607
1608 alg_region.type = coeff_blk.mem_type;
1609 alg_region.alg = alg_blk.id;
1610
1611 ret = wm_adsp_create_control(dsp, &alg_region,
1612 coeff_blk.offset,
1613 coeff_blk.len,
1614 coeff_blk.name,
Charles Keepax26c22a12015-04-20 13:52:45 +01001615 coeff_blk.name_len,
Stuart Henderson8eb084d2016-11-09 17:14:16 +00001616 coeff_blk.flags,
1617 coeff_blk.ctl_type);
Charles Keepax23237362015-04-13 13:28:02 +01001618 if (ret < 0)
1619 adsp_err(dsp, "Failed to create control: %.*s, %d\n",
1620 coeff_blk.name_len, coeff_blk.name, ret);
1621 }
1622
1623 return 0;
1624}
1625
Mark Brown2159ad932012-10-11 11:54:02 +09001626static int wm_adsp_load(struct wm_adsp *dsp)
1627{
Mark Browncf17c832013-01-30 14:37:23 +08001628 LIST_HEAD(buf_list);
Mark Brown2159ad932012-10-11 11:54:02 +09001629 const struct firmware *firmware;
1630 struct regmap *regmap = dsp->regmap;
1631 unsigned int pos = 0;
1632 const struct wmfw_header *header;
1633 const struct wmfw_adsp1_sizes *adsp1_sizes;
1634 const struct wmfw_adsp2_sizes *adsp2_sizes;
1635 const struct wmfw_footer *footer;
1636 const struct wmfw_region *region;
1637 const struct wm_adsp_region *mem;
1638 const char *region_name;
Richard Fitzgerald1cab2a82016-12-20 10:29:12 +00001639 char *file, *text = NULL;
Mark Browncf17c832013-01-30 14:37:23 +08001640 struct wm_adsp_buf *buf;
Mark Brown2159ad932012-10-11 11:54:02 +09001641 unsigned int reg;
1642 int regions = 0;
1643 int ret, offset, type, sizes;
1644
1645 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1646 if (file == NULL)
1647 return -ENOMEM;
1648
Richard Fitzgerald605391d2018-08-08 17:13:39 +01001649 snprintf(file, PAGE_SIZE, "%s-%s-%s.wmfw", dsp->part, dsp->fwf_name,
Mark Brown1023dbd2013-01-11 22:58:28 +00001650 wm_adsp_fw[dsp->fw].file);
Mark Brown2159ad932012-10-11 11:54:02 +09001651 file[PAGE_SIZE - 1] = '\0';
1652
1653 ret = request_firmware(&firmware, file, dsp->dev);
1654 if (ret != 0) {
1655 adsp_err(dsp, "Failed to request '%s'\n", file);
1656 goto out;
1657 }
1658 ret = -EINVAL;
1659
1660 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1661 if (pos >= firmware->size) {
1662 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1663 file, firmware->size);
1664 goto out_fw;
1665 }
1666
Charles Keepax7585a5b2015-12-08 16:08:25 +00001667 header = (void *)&firmware->data[0];
Mark Brown2159ad932012-10-11 11:54:02 +09001668
1669 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
1670 adsp_err(dsp, "%s: invalid magic\n", file);
1671 goto out_fw;
1672 }
1673
Charles Keepax23237362015-04-13 13:28:02 +01001674 switch (header->ver) {
1675 case 0:
Charles Keepaxc61e59f2015-04-13 13:28:05 +01001676 adsp_warn(dsp, "%s: Depreciated file format %d\n",
1677 file, header->ver);
1678 break;
Charles Keepax23237362015-04-13 13:28:02 +01001679 case 1:
Charles Keepaxcb5b57a2015-04-13 13:28:04 +01001680 case 2:
Charles Keepax23237362015-04-13 13:28:02 +01001681 break;
1682 default:
Mark Brown2159ad932012-10-11 11:54:02 +09001683 adsp_err(dsp, "%s: unknown file format %d\n",
1684 file, header->ver);
1685 goto out_fw;
1686 }
Charles Keepax23237362015-04-13 13:28:02 +01001687
Dimitris Papastamos36269922013-11-01 15:56:57 +00001688 adsp_info(dsp, "Firmware version: %d\n", header->ver);
Charles Keepax23237362015-04-13 13:28:02 +01001689 dsp->fw_ver = header->ver;
Mark Brown2159ad932012-10-11 11:54:02 +09001690
1691 if (header->core != dsp->type) {
1692 adsp_err(dsp, "%s: invalid core %d != %d\n",
1693 file, header->core, dsp->type);
1694 goto out_fw;
1695 }
1696
1697 switch (dsp->type) {
1698 case WMFW_ADSP1:
1699 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1700 adsp1_sizes = (void *)&(header[1]);
1701 footer = (void *)&(adsp1_sizes[1]);
1702 sizes = sizeof(*adsp1_sizes);
1703
1704 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
1705 file, le32_to_cpu(adsp1_sizes->dm),
1706 le32_to_cpu(adsp1_sizes->pm),
1707 le32_to_cpu(adsp1_sizes->zm));
1708 break;
1709
1710 case WMFW_ADSP2:
1711 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
1712 adsp2_sizes = (void *)&(header[1]);
1713 footer = (void *)&(adsp2_sizes[1]);
1714 sizes = sizeof(*adsp2_sizes);
1715
1716 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
1717 file, le32_to_cpu(adsp2_sizes->xm),
1718 le32_to_cpu(adsp2_sizes->ym),
1719 le32_to_cpu(adsp2_sizes->pm),
1720 le32_to_cpu(adsp2_sizes->zm));
1721 break;
1722
1723 default:
Takashi Iwai6c452bd2013-11-05 18:40:00 +01001724 WARN(1, "Unknown DSP type");
Mark Brown2159ad932012-10-11 11:54:02 +09001725 goto out_fw;
1726 }
1727
1728 if (le32_to_cpu(header->len) != sizeof(*header) +
1729 sizes + sizeof(*footer)) {
1730 adsp_err(dsp, "%s: unexpected header length %d\n",
1731 file, le32_to_cpu(header->len));
1732 goto out_fw;
1733 }
1734
1735 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
1736 le64_to_cpu(footer->timestamp));
1737
1738 while (pos < firmware->size &&
Ben Hutchings50dd2ea2017-12-08 16:15:20 +00001739 sizeof(*region) < firmware->size - pos) {
Mark Brown2159ad932012-10-11 11:54:02 +09001740 region = (void *)&(firmware->data[pos]);
1741 region_name = "Unknown";
1742 reg = 0;
1743 text = NULL;
1744 offset = le32_to_cpu(region->offset) & 0xffffff;
1745 type = be32_to_cpu(region->type) & 0xff;
1746 mem = wm_adsp_find_region(dsp, type);
Charles Keepax7585a5b2015-12-08 16:08:25 +00001747
Mark Brown2159ad932012-10-11 11:54:02 +09001748 switch (type) {
1749 case WMFW_NAME_TEXT:
1750 region_name = "Firmware name";
1751 text = kzalloc(le32_to_cpu(region->len) + 1,
1752 GFP_KERNEL);
1753 break;
Charles Keepax23237362015-04-13 13:28:02 +01001754 case WMFW_ALGORITHM_DATA:
1755 region_name = "Algorithm";
1756 ret = wm_adsp_parse_coeff(dsp, region);
1757 if (ret != 0)
1758 goto out_fw;
1759 break;
Mark Brown2159ad932012-10-11 11:54:02 +09001760 case WMFW_INFO_TEXT:
1761 region_name = "Information";
1762 text = kzalloc(le32_to_cpu(region->len) + 1,
1763 GFP_KERNEL);
1764 break;
1765 case WMFW_ABSOLUTE:
1766 region_name = "Absolute";
1767 reg = offset;
1768 break;
1769 case WMFW_ADSP1_PM:
Mark Brown2159ad932012-10-11 11:54:02 +09001770 case WMFW_ADSP1_DM:
Mark Brown2159ad932012-10-11 11:54:02 +09001771 case WMFW_ADSP2_XM:
Mark Brown2159ad932012-10-11 11:54:02 +09001772 case WMFW_ADSP2_YM:
Mark Brown2159ad932012-10-11 11:54:02 +09001773 case WMFW_ADSP1_ZM:
Richard Fitzgerald9ce5e6e2016-11-09 17:14:15 +00001774 region_name = wm_adsp_mem_region_name(type);
Mark Brown45b9ee72013-01-08 16:02:06 +00001775 reg = wm_adsp_region_to_reg(mem, offset);
Mark Brown2159ad932012-10-11 11:54:02 +09001776 break;
1777 default:
1778 adsp_warn(dsp,
1779 "%s.%d: Unknown region type %x at %d(%x)\n",
1780 file, regions, type, pos, pos);
1781 break;
1782 }
1783
1784 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1785 regions, le32_to_cpu(region->len), offset,
1786 region_name);
1787
Ben Hutchings50dd2ea2017-12-08 16:15:20 +00001788 if (le32_to_cpu(region->len) >
1789 firmware->size - pos - sizeof(*region)) {
Richard Fitzgerald1cab2a82016-12-20 10:29:12 +00001790 adsp_err(dsp,
1791 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
1792 file, regions, region_name,
1793 le32_to_cpu(region->len), firmware->size);
1794 ret = -EINVAL;
1795 goto out_fw;
1796 }
1797
Mark Brown2159ad932012-10-11 11:54:02 +09001798 if (text) {
1799 memcpy(text, region->data, le32_to_cpu(region->len));
1800 adsp_info(dsp, "%s: %s\n", file, text);
1801 kfree(text);
Richard Fitzgerald1cab2a82016-12-20 10:29:12 +00001802 text = NULL;
Mark Brown2159ad932012-10-11 11:54:02 +09001803 }
1804
1805 if (reg) {
Charles Keepaxcdcd7f72014-11-14 15:40:45 +00001806 buf = wm_adsp_buf_alloc(region->data,
1807 le32_to_cpu(region->len),
1808 &buf_list);
1809 if (!buf) {
1810 adsp_err(dsp, "Out of memory\n");
1811 ret = -ENOMEM;
1812 goto out_fw;
1813 }
Mark Browna76fefa2013-01-07 19:03:17 +00001814
Charles Keepaxcdcd7f72014-11-14 15:40:45 +00001815 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1816 le32_to_cpu(region->len));
1817 if (ret != 0) {
1818 adsp_err(dsp,
1819 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1820 file, regions,
1821 le32_to_cpu(region->len), offset,
1822 region_name, ret);
1823 goto out_fw;
Mark Brown2159ad932012-10-11 11:54:02 +09001824 }
1825 }
1826
1827 pos += le32_to_cpu(region->len) + sizeof(*region);
1828 regions++;
1829 }
Mark Browncf17c832013-01-30 14:37:23 +08001830
1831 ret = regmap_async_complete(regmap);
1832 if (ret != 0) {
1833 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1834 goto out_fw;
1835 }
1836
Mark Brown2159ad932012-10-11 11:54:02 +09001837 if (pos > firmware->size)
1838 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1839 file, regions, pos - firmware->size);
1840
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +01001841 wm_adsp_debugfs_save_wmfwname(dsp, file);
1842
Mark Brown2159ad932012-10-11 11:54:02 +09001843out_fw:
Mark Browncf17c832013-01-30 14:37:23 +08001844 regmap_async_complete(regmap);
1845 wm_adsp_buf_free(&buf_list);
Mark Brown2159ad932012-10-11 11:54:02 +09001846 release_firmware(firmware);
Richard Fitzgerald1cab2a82016-12-20 10:29:12 +00001847 kfree(text);
Mark Brown2159ad932012-10-11 11:54:02 +09001848out:
1849 kfree(file);
1850
1851 return ret;
1852}
1853
Charles Keepax23237362015-04-13 13:28:02 +01001854static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
1855 const struct wm_adsp_alg_region *alg_region)
1856{
1857 struct wm_coeff_ctl *ctl;
1858
1859 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1860 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
1861 alg_region->alg == ctl->alg_region.alg &&
1862 alg_region->type == ctl->alg_region.type) {
1863 ctl->alg_region.base = alg_region->base;
1864 }
1865 }
1866}
1867
Charles Keepax3809f002015-04-13 13:27:54 +01001868static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
Charles Keepax7f7cca02018-06-20 11:56:21 +01001869 const struct wm_adsp_region *mem,
Charles Keepaxb618a1852015-04-13 13:27:53 +01001870 unsigned int pos, unsigned int len)
Mark Browndb405172012-10-26 19:30:40 +01001871{
Charles Keepaxb618a1852015-04-13 13:27:53 +01001872 void *alg;
Charles Keepax7f7cca02018-06-20 11:56:21 +01001873 unsigned int reg;
Charles Keepaxb618a1852015-04-13 13:27:53 +01001874 int ret;
Mark Browndb405172012-10-26 19:30:40 +01001875 __be32 val;
Mark Browndb405172012-10-26 19:30:40 +01001876
Charles Keepax3809f002015-04-13 13:27:54 +01001877 if (n_algs == 0) {
Mark Browndb405172012-10-26 19:30:40 +01001878 adsp_err(dsp, "No algorithms\n");
Charles Keepaxb618a1852015-04-13 13:27:53 +01001879 return ERR_PTR(-EINVAL);
Mark Browndb405172012-10-26 19:30:40 +01001880 }
1881
Charles Keepax3809f002015-04-13 13:27:54 +01001882 if (n_algs > 1024) {
1883 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
Charles Keepaxb618a1852015-04-13 13:27:53 +01001884 return ERR_PTR(-EINVAL);
Mark Brownd62f4bc2012-12-19 14:00:30 +00001885 }
1886
Mark Browndb405172012-10-26 19:30:40 +01001887 /* Read the terminator first to validate the length */
Charles Keepax7f7cca02018-06-20 11:56:21 +01001888 reg = wm_adsp_region_to_reg(mem, pos + len);
1889
1890 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
Mark Browndb405172012-10-26 19:30:40 +01001891 if (ret != 0) {
1892 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1893 ret);
Charles Keepaxb618a1852015-04-13 13:27:53 +01001894 return ERR_PTR(ret);
Mark Browndb405172012-10-26 19:30:40 +01001895 }
1896
1897 if (be32_to_cpu(val) != 0xbedead)
Richard Fitzgerald503ada82017-05-26 10:47:07 +01001898 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n",
Charles Keepax7f7cca02018-06-20 11:56:21 +01001899 reg, be32_to_cpu(val));
1900
1901 /* Convert length from DSP words to bytes */
1902 len *= sizeof(u32);
Mark Browndb405172012-10-26 19:30:40 +01001903
Charles Keepax517ee742018-07-19 11:50:35 +01001904 alg = kzalloc(len, GFP_KERNEL | GFP_DMA);
Mark Browndb405172012-10-26 19:30:40 +01001905 if (!alg)
Charles Keepaxb618a1852015-04-13 13:27:53 +01001906 return ERR_PTR(-ENOMEM);
Mark Browndb405172012-10-26 19:30:40 +01001907
Charles Keepax7f7cca02018-06-20 11:56:21 +01001908 reg = wm_adsp_region_to_reg(mem, pos);
1909
1910 ret = regmap_raw_read(dsp->regmap, reg, alg, len);
Mark Browndb405172012-10-26 19:30:40 +01001911 if (ret != 0) {
Charles Keepax7d00cd92016-02-19 14:44:43 +00001912 adsp_err(dsp, "Failed to read algorithm list: %d\n", ret);
Charles Keepaxb618a1852015-04-13 13:27:53 +01001913 kfree(alg);
1914 return ERR_PTR(ret);
Mark Browndb405172012-10-26 19:30:40 +01001915 }
1916
Charles Keepaxb618a1852015-04-13 13:27:53 +01001917 return alg;
1918}
1919
Charles Keepax14197092015-12-15 11:29:43 +00001920static struct wm_adsp_alg_region *
1921 wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id)
1922{
1923 struct wm_adsp_alg_region *alg_region;
1924
1925 list_for_each_entry(alg_region, &dsp->alg_regions, list) {
1926 if (id == alg_region->alg && type == alg_region->type)
1927 return alg_region;
1928 }
1929
1930 return NULL;
1931}
1932
Charles Keepaxd9d20e12015-04-13 13:27:59 +01001933static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
1934 int type, __be32 id,
1935 __be32 base)
1936{
1937 struct wm_adsp_alg_region *alg_region;
1938
1939 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
1940 if (!alg_region)
1941 return ERR_PTR(-ENOMEM);
1942
1943 alg_region->type = type;
1944 alg_region->alg = be32_to_cpu(id);
1945 alg_region->base = be32_to_cpu(base);
1946
1947 list_add_tail(&alg_region->list, &dsp->alg_regions);
1948
Charles Keepax23237362015-04-13 13:28:02 +01001949 if (dsp->fw_ver > 0)
1950 wm_adsp_ctl_fixup_base(dsp, alg_region);
1951
Charles Keepaxd9d20e12015-04-13 13:27:59 +01001952 return alg_region;
1953}
1954
Richard Fitzgerald56574d52016-04-27 14:58:29 +01001955static void wm_adsp_free_alg_regions(struct wm_adsp *dsp)
1956{
1957 struct wm_adsp_alg_region *alg_region;
1958
1959 while (!list_empty(&dsp->alg_regions)) {
1960 alg_region = list_first_entry(&dsp->alg_regions,
1961 struct wm_adsp_alg_region,
1962 list);
1963 list_del(&alg_region->list);
1964 kfree(alg_region);
1965 }
1966}
1967
Charles Keepaxb618a1852015-04-13 13:27:53 +01001968static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
1969{
1970 struct wmfw_adsp1_id_hdr adsp1_id;
1971 struct wmfw_adsp1_alg_hdr *adsp1_alg;
Charles Keepax3809f002015-04-13 13:27:54 +01001972 struct wm_adsp_alg_region *alg_region;
Charles Keepaxb618a1852015-04-13 13:27:53 +01001973 const struct wm_adsp_region *mem;
1974 unsigned int pos, len;
Charles Keepax3809f002015-04-13 13:27:54 +01001975 size_t n_algs;
Charles Keepaxb618a1852015-04-13 13:27:53 +01001976 int i, ret;
1977
1978 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
1979 if (WARN_ON(!mem))
1980 return -EINVAL;
1981
1982 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
1983 sizeof(adsp1_id));
1984 if (ret != 0) {
1985 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1986 ret);
1987 return ret;
1988 }
1989
Charles Keepax3809f002015-04-13 13:27:54 +01001990 n_algs = be32_to_cpu(adsp1_id.n_algs);
Charles Keepaxb618a1852015-04-13 13:27:53 +01001991 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
1992 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1993 dsp->fw_id,
1994 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
1995 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
1996 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
Charles Keepax3809f002015-04-13 13:27:54 +01001997 n_algs);
Charles Keepaxb618a1852015-04-13 13:27:53 +01001998
Charles Keepaxd9d20e12015-04-13 13:27:59 +01001999 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
2000 adsp1_id.fw.id, adsp1_id.zm);
2001 if (IS_ERR(alg_region))
2002 return PTR_ERR(alg_region);
Charles Keepaxb618a1852015-04-13 13:27:53 +01002003
Charles Keepaxd9d20e12015-04-13 13:27:59 +01002004 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
2005 adsp1_id.fw.id, adsp1_id.dm);
2006 if (IS_ERR(alg_region))
2007 return PTR_ERR(alg_region);
Charles Keepaxb618a1852015-04-13 13:27:53 +01002008
Charles Keepax7f7cca02018-06-20 11:56:21 +01002009 /* Calculate offset and length in DSP words */
2010 pos = sizeof(adsp1_id) / sizeof(u32);
2011 len = (sizeof(*adsp1_alg) * n_algs) / sizeof(u32);
Charles Keepaxb618a1852015-04-13 13:27:53 +01002012
Charles Keepax7f7cca02018-06-20 11:56:21 +01002013 adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
Charles Keepaxb618a1852015-04-13 13:27:53 +01002014 if (IS_ERR(adsp1_alg))
2015 return PTR_ERR(adsp1_alg);
Mark Browndb405172012-10-26 19:30:40 +01002016
Charles Keepax3809f002015-04-13 13:27:54 +01002017 for (i = 0; i < n_algs; i++) {
Charles Keepaxb618a1852015-04-13 13:27:53 +01002018 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
2019 i, be32_to_cpu(adsp1_alg[i].alg.id),
2020 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
2021 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
2022 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
2023 be32_to_cpu(adsp1_alg[i].dm),
2024 be32_to_cpu(adsp1_alg[i].zm));
Mark Brown471f4882013-01-08 16:09:31 +00002025
Charles Keepaxd9d20e12015-04-13 13:27:59 +01002026 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
2027 adsp1_alg[i].alg.id,
2028 adsp1_alg[i].dm);
2029 if (IS_ERR(alg_region)) {
2030 ret = PTR_ERR(alg_region);
Charles Keepaxb618a1852015-04-13 13:27:53 +01002031 goto out;
2032 }
Charles Keepax23237362015-04-13 13:28:02 +01002033 if (dsp->fw_ver == 0) {
2034 if (i + 1 < n_algs) {
2035 len = be32_to_cpu(adsp1_alg[i + 1].dm);
2036 len -= be32_to_cpu(adsp1_alg[i].dm);
2037 len *= 4;
2038 wm_adsp_create_control(dsp, alg_region, 0,
Stuart Henderson8eb084d2016-11-09 17:14:16 +00002039 len, NULL, 0, 0,
2040 SNDRV_CTL_ELEM_TYPE_BYTES);
Charles Keepax23237362015-04-13 13:28:02 +01002041 } else {
2042 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
2043 be32_to_cpu(adsp1_alg[i].alg.id));
2044 }
Charles Keepaxb618a1852015-04-13 13:27:53 +01002045 }
Mark Brown471f4882013-01-08 16:09:31 +00002046
Charles Keepaxd9d20e12015-04-13 13:27:59 +01002047 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
2048 adsp1_alg[i].alg.id,
2049 adsp1_alg[i].zm);
2050 if (IS_ERR(alg_region)) {
2051 ret = PTR_ERR(alg_region);
Charles Keepaxb618a1852015-04-13 13:27:53 +01002052 goto out;
2053 }
Charles Keepax23237362015-04-13 13:28:02 +01002054 if (dsp->fw_ver == 0) {
2055 if (i + 1 < n_algs) {
2056 len = be32_to_cpu(adsp1_alg[i + 1].zm);
2057 len -= be32_to_cpu(adsp1_alg[i].zm);
2058 len *= 4;
2059 wm_adsp_create_control(dsp, alg_region, 0,
Stuart Henderson8eb084d2016-11-09 17:14:16 +00002060 len, NULL, 0, 0,
2061 SNDRV_CTL_ELEM_TYPE_BYTES);
Charles Keepax23237362015-04-13 13:28:02 +01002062 } else {
2063 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2064 be32_to_cpu(adsp1_alg[i].alg.id));
2065 }
Mark Browndb405172012-10-26 19:30:40 +01002066 }
2067 }
2068
2069out:
Charles Keepaxb618a1852015-04-13 13:27:53 +01002070 kfree(adsp1_alg);
2071 return ret;
2072}
2073
2074static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
2075{
2076 struct wmfw_adsp2_id_hdr adsp2_id;
2077 struct wmfw_adsp2_alg_hdr *adsp2_alg;
Charles Keepax3809f002015-04-13 13:27:54 +01002078 struct wm_adsp_alg_region *alg_region;
Charles Keepaxb618a1852015-04-13 13:27:53 +01002079 const struct wm_adsp_region *mem;
2080 unsigned int pos, len;
Charles Keepax3809f002015-04-13 13:27:54 +01002081 size_t n_algs;
Charles Keepaxb618a1852015-04-13 13:27:53 +01002082 int i, ret;
2083
2084 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
2085 if (WARN_ON(!mem))
2086 return -EINVAL;
2087
2088 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
2089 sizeof(adsp2_id));
2090 if (ret != 0) {
2091 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2092 ret);
2093 return ret;
2094 }
2095
Charles Keepax3809f002015-04-13 13:27:54 +01002096 n_algs = be32_to_cpu(adsp2_id.n_algs);
Charles Keepaxb618a1852015-04-13 13:27:53 +01002097 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +01002098 dsp->fw_id_version = be32_to_cpu(adsp2_id.fw.ver);
Charles Keepaxb618a1852015-04-13 13:27:53 +01002099 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
2100 dsp->fw_id,
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +01002101 (dsp->fw_id_version & 0xff0000) >> 16,
2102 (dsp->fw_id_version & 0xff00) >> 8,
2103 dsp->fw_id_version & 0xff,
Charles Keepax3809f002015-04-13 13:27:54 +01002104 n_algs);
Charles Keepaxb618a1852015-04-13 13:27:53 +01002105
Charles Keepaxd9d20e12015-04-13 13:27:59 +01002106 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2107 adsp2_id.fw.id, adsp2_id.xm);
2108 if (IS_ERR(alg_region))
2109 return PTR_ERR(alg_region);
Charles Keepaxb618a1852015-04-13 13:27:53 +01002110
Charles Keepaxd9d20e12015-04-13 13:27:59 +01002111 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2112 adsp2_id.fw.id, adsp2_id.ym);
2113 if (IS_ERR(alg_region))
2114 return PTR_ERR(alg_region);
Charles Keepaxb618a1852015-04-13 13:27:53 +01002115
Charles Keepaxd9d20e12015-04-13 13:27:59 +01002116 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2117 adsp2_id.fw.id, adsp2_id.zm);
2118 if (IS_ERR(alg_region))
2119 return PTR_ERR(alg_region);
Charles Keepaxb618a1852015-04-13 13:27:53 +01002120
Charles Keepax7f7cca02018-06-20 11:56:21 +01002121 /* Calculate offset and length in DSP words */
2122 pos = sizeof(adsp2_id) / sizeof(u32);
2123 len = (sizeof(*adsp2_alg) * n_algs) / sizeof(u32);
Charles Keepaxb618a1852015-04-13 13:27:53 +01002124
Charles Keepax7f7cca02018-06-20 11:56:21 +01002125 adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
Charles Keepaxb618a1852015-04-13 13:27:53 +01002126 if (IS_ERR(adsp2_alg))
2127 return PTR_ERR(adsp2_alg);
2128
Charles Keepax3809f002015-04-13 13:27:54 +01002129 for (i = 0; i < n_algs; i++) {
Charles Keepaxb618a1852015-04-13 13:27:53 +01002130 adsp_info(dsp,
2131 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
2132 i, be32_to_cpu(adsp2_alg[i].alg.id),
2133 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
2134 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
2135 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
2136 be32_to_cpu(adsp2_alg[i].xm),
2137 be32_to_cpu(adsp2_alg[i].ym),
2138 be32_to_cpu(adsp2_alg[i].zm));
2139
Charles Keepaxd9d20e12015-04-13 13:27:59 +01002140 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2141 adsp2_alg[i].alg.id,
2142 adsp2_alg[i].xm);
2143 if (IS_ERR(alg_region)) {
2144 ret = PTR_ERR(alg_region);
Charles Keepaxb618a1852015-04-13 13:27:53 +01002145 goto out;
2146 }
Charles Keepax23237362015-04-13 13:28:02 +01002147 if (dsp->fw_ver == 0) {
2148 if (i + 1 < n_algs) {
2149 len = be32_to_cpu(adsp2_alg[i + 1].xm);
2150 len -= be32_to_cpu(adsp2_alg[i].xm);
2151 len *= 4;
2152 wm_adsp_create_control(dsp, alg_region, 0,
Stuart Henderson8eb084d2016-11-09 17:14:16 +00002153 len, NULL, 0, 0,
2154 SNDRV_CTL_ELEM_TYPE_BYTES);
Charles Keepax23237362015-04-13 13:28:02 +01002155 } else {
2156 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
2157 be32_to_cpu(adsp2_alg[i].alg.id));
2158 }
Charles Keepaxb618a1852015-04-13 13:27:53 +01002159 }
2160
Charles Keepaxd9d20e12015-04-13 13:27:59 +01002161 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2162 adsp2_alg[i].alg.id,
2163 adsp2_alg[i].ym);
2164 if (IS_ERR(alg_region)) {
2165 ret = PTR_ERR(alg_region);
Charles Keepaxb618a1852015-04-13 13:27:53 +01002166 goto out;
2167 }
Charles Keepax23237362015-04-13 13:28:02 +01002168 if (dsp->fw_ver == 0) {
2169 if (i + 1 < n_algs) {
2170 len = be32_to_cpu(adsp2_alg[i + 1].ym);
2171 len -= be32_to_cpu(adsp2_alg[i].ym);
2172 len *= 4;
2173 wm_adsp_create_control(dsp, alg_region, 0,
Stuart Henderson8eb084d2016-11-09 17:14:16 +00002174 len, NULL, 0, 0,
2175 SNDRV_CTL_ELEM_TYPE_BYTES);
Charles Keepax23237362015-04-13 13:28:02 +01002176 } else {
2177 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
2178 be32_to_cpu(adsp2_alg[i].alg.id));
2179 }
Charles Keepaxb618a1852015-04-13 13:27:53 +01002180 }
2181
Charles Keepaxd9d20e12015-04-13 13:27:59 +01002182 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2183 adsp2_alg[i].alg.id,
2184 adsp2_alg[i].zm);
2185 if (IS_ERR(alg_region)) {
2186 ret = PTR_ERR(alg_region);
Charles Keepaxb618a1852015-04-13 13:27:53 +01002187 goto out;
2188 }
Charles Keepax23237362015-04-13 13:28:02 +01002189 if (dsp->fw_ver == 0) {
2190 if (i + 1 < n_algs) {
2191 len = be32_to_cpu(adsp2_alg[i + 1].zm);
2192 len -= be32_to_cpu(adsp2_alg[i].zm);
2193 len *= 4;
2194 wm_adsp_create_control(dsp, alg_region, 0,
Stuart Henderson8eb084d2016-11-09 17:14:16 +00002195 len, NULL, 0, 0,
2196 SNDRV_CTL_ELEM_TYPE_BYTES);
Charles Keepax23237362015-04-13 13:28:02 +01002197 } else {
2198 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2199 be32_to_cpu(adsp2_alg[i].alg.id));
2200 }
Charles Keepaxb618a1852015-04-13 13:27:53 +01002201 }
2202 }
2203
2204out:
2205 kfree(adsp2_alg);
Mark Browndb405172012-10-26 19:30:40 +01002206 return ret;
2207}
2208
Mark Brown2159ad932012-10-11 11:54:02 +09002209static int wm_adsp_load_coeff(struct wm_adsp *dsp)
2210{
Mark Browncf17c832013-01-30 14:37:23 +08002211 LIST_HEAD(buf_list);
Mark Brown2159ad932012-10-11 11:54:02 +09002212 struct regmap *regmap = dsp->regmap;
2213 struct wmfw_coeff_hdr *hdr;
2214 struct wmfw_coeff_item *blk;
2215 const struct firmware *firmware;
Mark Brown471f4882013-01-08 16:09:31 +00002216 const struct wm_adsp_region *mem;
2217 struct wm_adsp_alg_region *alg_region;
Mark Brown2159ad932012-10-11 11:54:02 +09002218 const char *region_name;
2219 int ret, pos, blocks, type, offset, reg;
2220 char *file;
Mark Browncf17c832013-01-30 14:37:23 +08002221 struct wm_adsp_buf *buf;
Mark Brown2159ad932012-10-11 11:54:02 +09002222
2223 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
2224 if (file == NULL)
2225 return -ENOMEM;
2226
Richard Fitzgerald605391d2018-08-08 17:13:39 +01002227 snprintf(file, PAGE_SIZE, "%s-%s-%s.bin", dsp->part, dsp->fwf_name,
Mark Brown1023dbd2013-01-11 22:58:28 +00002228 wm_adsp_fw[dsp->fw].file);
Mark Brown2159ad932012-10-11 11:54:02 +09002229 file[PAGE_SIZE - 1] = '\0';
2230
2231 ret = request_firmware(&firmware, file, dsp->dev);
2232 if (ret != 0) {
2233 adsp_warn(dsp, "Failed to request '%s'\n", file);
2234 ret = 0;
2235 goto out;
2236 }
2237 ret = -EINVAL;
2238
2239 if (sizeof(*hdr) >= firmware->size) {
2240 adsp_err(dsp, "%s: file too short, %zu bytes\n",
2241 file, firmware->size);
2242 goto out_fw;
2243 }
2244
Charles Keepax7585a5b2015-12-08 16:08:25 +00002245 hdr = (void *)&firmware->data[0];
Mark Brown2159ad932012-10-11 11:54:02 +09002246 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
2247 adsp_err(dsp, "%s: invalid magic\n", file);
Charles Keepaxa4cdbec2013-01-21 09:02:31 +00002248 goto out_fw;
Mark Brown2159ad932012-10-11 11:54:02 +09002249 }
2250
Mark Brownc7123262013-01-16 16:59:04 +09002251 switch (be32_to_cpu(hdr->rev) & 0xff) {
2252 case 1:
2253 break;
2254 default:
2255 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
2256 file, be32_to_cpu(hdr->rev) & 0xff);
2257 ret = -EINVAL;
2258 goto out_fw;
2259 }
2260
Mark Brown2159ad932012-10-11 11:54:02 +09002261 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
2262 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
2263 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
2264 le32_to_cpu(hdr->ver) & 0xff);
2265
2266 pos = le32_to_cpu(hdr->len);
2267
2268 blocks = 0;
2269 while (pos < firmware->size &&
Ben Hutchings50dd2ea2017-12-08 16:15:20 +00002270 sizeof(*blk) < firmware->size - pos) {
Charles Keepax7585a5b2015-12-08 16:08:25 +00002271 blk = (void *)(&firmware->data[pos]);
Mark Brown2159ad932012-10-11 11:54:02 +09002272
Mark Brownc7123262013-01-16 16:59:04 +09002273 type = le16_to_cpu(blk->type);
2274 offset = le16_to_cpu(blk->offset);
Mark Brown2159ad932012-10-11 11:54:02 +09002275
2276 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
2277 file, blocks, le32_to_cpu(blk->id),
2278 (le32_to_cpu(blk->ver) >> 16) & 0xff,
2279 (le32_to_cpu(blk->ver) >> 8) & 0xff,
2280 le32_to_cpu(blk->ver) & 0xff);
2281 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
2282 file, blocks, le32_to_cpu(blk->len), offset, type);
2283
2284 reg = 0;
2285 region_name = "Unknown";
2286 switch (type) {
Mark Brownc7123262013-01-16 16:59:04 +09002287 case (WMFW_NAME_TEXT << 8):
2288 case (WMFW_INFO_TEXT << 8):
Mark Brown2159ad932012-10-11 11:54:02 +09002289 break;
Mark Brownc7123262013-01-16 16:59:04 +09002290 case (WMFW_ABSOLUTE << 8):
Mark Brownf395a212013-03-05 22:39:54 +08002291 /*
2292 * Old files may use this for global
2293 * coefficients.
2294 */
2295 if (le32_to_cpu(blk->id) == dsp->fw_id &&
2296 offset == 0) {
2297 region_name = "global coefficients";
2298 mem = wm_adsp_find_region(dsp, type);
2299 if (!mem) {
2300 adsp_err(dsp, "No ZM\n");
2301 break;
2302 }
2303 reg = wm_adsp_region_to_reg(mem, 0);
2304
2305 } else {
2306 region_name = "register";
2307 reg = offset;
2308 }
Mark Brown2159ad932012-10-11 11:54:02 +09002309 break;
Mark Brown471f4882013-01-08 16:09:31 +00002310
2311 case WMFW_ADSP1_DM:
2312 case WMFW_ADSP1_ZM:
2313 case WMFW_ADSP2_XM:
2314 case WMFW_ADSP2_YM:
2315 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
2316 file, blocks, le32_to_cpu(blk->len),
2317 type, le32_to_cpu(blk->id));
2318
2319 mem = wm_adsp_find_region(dsp, type);
2320 if (!mem) {
2321 adsp_err(dsp, "No base for region %x\n", type);
2322 break;
2323 }
2324
Charles Keepax14197092015-12-15 11:29:43 +00002325 alg_region = wm_adsp_find_alg_region(dsp, type,
2326 le32_to_cpu(blk->id));
2327 if (alg_region) {
2328 reg = alg_region->base;
2329 reg = wm_adsp_region_to_reg(mem, reg);
2330 reg += offset;
2331 } else {
Mark Brown471f4882013-01-08 16:09:31 +00002332 adsp_err(dsp, "No %x for algorithm %x\n",
2333 type, le32_to_cpu(blk->id));
Charles Keepax14197092015-12-15 11:29:43 +00002334 }
Mark Brown471f4882013-01-08 16:09:31 +00002335 break;
2336
Mark Brown2159ad932012-10-11 11:54:02 +09002337 default:
Mark Brown25c62f7e2013-01-20 19:02:19 +09002338 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
2339 file, blocks, type, pos);
Mark Brown2159ad932012-10-11 11:54:02 +09002340 break;
2341 }
2342
2343 if (reg) {
Ben Hutchings50dd2ea2017-12-08 16:15:20 +00002344 if (le32_to_cpu(blk->len) >
2345 firmware->size - pos - sizeof(*blk)) {
Richard Fitzgerald1cab2a82016-12-20 10:29:12 +00002346 adsp_err(dsp,
2347 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
2348 file, blocks, region_name,
2349 le32_to_cpu(blk->len),
2350 firmware->size);
2351 ret = -EINVAL;
2352 goto out_fw;
2353 }
2354
Mark Browncf17c832013-01-30 14:37:23 +08002355 buf = wm_adsp_buf_alloc(blk->data,
2356 le32_to_cpu(blk->len),
2357 &buf_list);
Mark Browna76fefa2013-01-07 19:03:17 +00002358 if (!buf) {
2359 adsp_err(dsp, "Out of memory\n");
Wei Yongjunf4b82812013-03-12 00:23:15 +08002360 ret = -ENOMEM;
2361 goto out_fw;
Mark Browna76fefa2013-01-07 19:03:17 +00002362 }
2363
Mark Brown20da6d52013-01-12 19:58:17 +00002364 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
2365 file, blocks, le32_to_cpu(blk->len),
2366 reg);
Mark Browncf17c832013-01-30 14:37:23 +08002367 ret = regmap_raw_write_async(regmap, reg, buf->buf,
2368 le32_to_cpu(blk->len));
Mark Brown2159ad932012-10-11 11:54:02 +09002369 if (ret != 0) {
2370 adsp_err(dsp,
Dimitris Papastamos43bc3bf2013-11-01 15:56:52 +00002371 "%s.%d: Failed to write to %x in %s: %d\n",
2372 file, blocks, reg, region_name, ret);
Mark Brown2159ad932012-10-11 11:54:02 +09002373 }
2374 }
2375
Charles Keepaxbe951012015-02-16 15:25:49 +00002376 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
Mark Brown2159ad932012-10-11 11:54:02 +09002377 blocks++;
2378 }
2379
Mark Browncf17c832013-01-30 14:37:23 +08002380 ret = regmap_async_complete(regmap);
2381 if (ret != 0)
2382 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
2383
Mark Brown2159ad932012-10-11 11:54:02 +09002384 if (pos > firmware->size)
2385 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
2386 file, blocks, pos - firmware->size);
2387
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +01002388 wm_adsp_debugfs_save_binname(dsp, file);
2389
Mark Brown2159ad932012-10-11 11:54:02 +09002390out_fw:
Charles Keepax9da7a5a2014-11-17 10:48:21 +00002391 regmap_async_complete(regmap);
Mark Brown2159ad932012-10-11 11:54:02 +09002392 release_firmware(firmware);
Mark Browncf17c832013-01-30 14:37:23 +08002393 wm_adsp_buf_free(&buf_list);
Mark Brown2159ad932012-10-11 11:54:02 +09002394out:
2395 kfree(file);
Wei Yongjunf4b82812013-03-12 00:23:15 +08002396 return ret;
Mark Brown2159ad932012-10-11 11:54:02 +09002397}
2398
Richard Fitzgerald605391d2018-08-08 17:13:39 +01002399static int wm_adsp_create_name(struct wm_adsp *dsp)
2400{
2401 char *p;
2402
2403 if (!dsp->name) {
2404 dsp->name = devm_kasprintf(dsp->dev, GFP_KERNEL, "DSP%d",
2405 dsp->num);
2406 if (!dsp->name)
2407 return -ENOMEM;
2408 }
2409
2410 if (!dsp->fwf_name) {
2411 p = devm_kstrdup(dsp->dev, dsp->name, GFP_KERNEL);
2412 if (!p)
2413 return -ENOMEM;
2414
2415 dsp->fwf_name = p;
2416 for (; *p != 0; ++p)
2417 *p = tolower(*p);
2418 }
2419
2420 return 0;
2421}
2422
Richard Fitzgeralddcad34f2018-11-12 13:36:39 +00002423static int wm_adsp_common_init(struct wm_adsp *dsp)
Mark Brown5e7a7a22013-01-16 10:03:56 +09002424{
Richard Fitzgerald605391d2018-08-08 17:13:39 +01002425 int ret;
2426
2427 ret = wm_adsp_create_name(dsp);
2428 if (ret)
2429 return ret;
2430
Charles Keepax3809f002015-04-13 13:27:54 +01002431 INIT_LIST_HEAD(&dsp->alg_regions);
Richard Fitzgeralddcad34f2018-11-12 13:36:39 +00002432 INIT_LIST_HEAD(&dsp->ctl_list);
Mark Brown5e7a7a22013-01-16 10:03:56 +09002433
Charles Keepax078e7182015-12-08 16:08:26 +00002434 mutex_init(&dsp->pwr_lock);
2435
Mark Brown5e7a7a22013-01-16 10:03:56 +09002436 return 0;
2437}
Richard Fitzgeralddcad34f2018-11-12 13:36:39 +00002438
2439int wm_adsp1_init(struct wm_adsp *dsp)
2440{
2441 return wm_adsp_common_init(dsp);
2442}
Mark Brown5e7a7a22013-01-16 10:03:56 +09002443EXPORT_SYMBOL_GPL(wm_adsp1_init);
2444
Mark Brown2159ad932012-10-11 11:54:02 +09002445int wm_adsp1_event(struct snd_soc_dapm_widget *w,
2446 struct snd_kcontrol *kcontrol,
2447 int event)
2448{
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +00002449 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2450 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
Mark Brown2159ad932012-10-11 11:54:02 +09002451 struct wm_adsp *dsp = &dsps[w->shift];
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01002452 struct wm_coeff_ctl *ctl;
Mark Brown2159ad932012-10-11 11:54:02 +09002453 int ret;
Charles Keepax7585a5b2015-12-08 16:08:25 +00002454 unsigned int val;
Mark Brown2159ad932012-10-11 11:54:02 +09002455
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +00002456 dsp->component = component;
Dimitris Papastamos92bb4c32013-08-01 11:11:28 +01002457
Charles Keepax078e7182015-12-08 16:08:26 +00002458 mutex_lock(&dsp->pwr_lock);
2459
Mark Brown2159ad932012-10-11 11:54:02 +09002460 switch (event) {
2461 case SND_SOC_DAPM_POST_PMU:
2462 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2463 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
2464
Chris Rattray94e205b2013-01-18 08:43:09 +00002465 /*
2466 * For simplicity set the DSP clock rate to be the
2467 * SYSCLK rate rather than making it configurable.
2468 */
Charles Keepax7585a5b2015-12-08 16:08:25 +00002469 if (dsp->sysclk_reg) {
Chris Rattray94e205b2013-01-18 08:43:09 +00002470 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
2471 if (ret != 0) {
2472 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
2473 ret);
Charles Keepax078e7182015-12-08 16:08:26 +00002474 goto err_mutex;
Chris Rattray94e205b2013-01-18 08:43:09 +00002475 }
2476
Charles Keepax7d00cd92016-02-19 14:44:43 +00002477 val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift;
Chris Rattray94e205b2013-01-18 08:43:09 +00002478
2479 ret = regmap_update_bits(dsp->regmap,
2480 dsp->base + ADSP1_CONTROL_31,
2481 ADSP1_CLK_SEL_MASK, val);
2482 if (ret != 0) {
2483 adsp_err(dsp, "Failed to set clock rate: %d\n",
2484 ret);
Charles Keepax078e7182015-12-08 16:08:26 +00002485 goto err_mutex;
Chris Rattray94e205b2013-01-18 08:43:09 +00002486 }
2487 }
2488
Mark Brown2159ad932012-10-11 11:54:02 +09002489 ret = wm_adsp_load(dsp);
2490 if (ret != 0)
Charles Keepax078e7182015-12-08 16:08:26 +00002491 goto err_ena;
Mark Brown2159ad932012-10-11 11:54:02 +09002492
Charles Keepaxb618a1852015-04-13 13:27:53 +01002493 ret = wm_adsp1_setup_algs(dsp);
Mark Browndb405172012-10-26 19:30:40 +01002494 if (ret != 0)
Charles Keepax078e7182015-12-08 16:08:26 +00002495 goto err_ena;
Mark Browndb405172012-10-26 19:30:40 +01002496
Mark Brown2159ad932012-10-11 11:54:02 +09002497 ret = wm_adsp_load_coeff(dsp);
2498 if (ret != 0)
Charles Keepax078e7182015-12-08 16:08:26 +00002499 goto err_ena;
Mark Brown2159ad932012-10-11 11:54:02 +09002500
Dimitris Papastamos0c2e3f32013-05-28 12:01:50 +01002501 /* Initialize caches for enabled and unset controls */
Dimitris Papastamos81ad93e2013-07-29 13:51:59 +01002502 ret = wm_coeff_init_control_caches(dsp);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01002503 if (ret != 0)
Charles Keepax078e7182015-12-08 16:08:26 +00002504 goto err_ena;
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01002505
Dimitris Papastamos0c2e3f32013-05-28 12:01:50 +01002506 /* Sync set controls */
Dimitris Papastamos81ad93e2013-07-29 13:51:59 +01002507 ret = wm_coeff_sync_controls(dsp);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01002508 if (ret != 0)
Charles Keepax078e7182015-12-08 16:08:26 +00002509 goto err_ena;
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01002510
Charles Keepax28823eb2016-09-20 13:52:32 +01002511 dsp->booted = true;
2512
Mark Brown2159ad932012-10-11 11:54:02 +09002513 /* Start the core running */
2514 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2515 ADSP1_CORE_ENA | ADSP1_START,
2516 ADSP1_CORE_ENA | ADSP1_START);
Charles Keepax28823eb2016-09-20 13:52:32 +01002517
2518 dsp->running = true;
Mark Brown2159ad932012-10-11 11:54:02 +09002519 break;
2520
2521 case SND_SOC_DAPM_PRE_PMD:
Charles Keepax28823eb2016-09-20 13:52:32 +01002522 dsp->running = false;
2523 dsp->booted = false;
2524
Mark Brown2159ad932012-10-11 11:54:02 +09002525 /* Halt the core */
2526 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2527 ADSP1_CORE_ENA | ADSP1_START, 0);
2528
2529 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
2530 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
2531
2532 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2533 ADSP1_SYS_ENA, 0);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01002534
Dimitris Papastamos81ad93e2013-07-29 13:51:59 +01002535 list_for_each_entry(ctl, &dsp->ctl_list, list)
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01002536 ctl->enabled = 0;
Dimitris Papastamosb0101b42013-11-01 15:56:56 +00002537
Richard Fitzgerald56574d52016-04-27 14:58:29 +01002538
2539 wm_adsp_free_alg_regions(dsp);
Mark Brown2159ad932012-10-11 11:54:02 +09002540 break;
2541
2542 default:
2543 break;
2544 }
2545
Charles Keepax078e7182015-12-08 16:08:26 +00002546 mutex_unlock(&dsp->pwr_lock);
2547
Mark Brown2159ad932012-10-11 11:54:02 +09002548 return 0;
2549
Charles Keepax078e7182015-12-08 16:08:26 +00002550err_ena:
Mark Brown2159ad932012-10-11 11:54:02 +09002551 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2552 ADSP1_SYS_ENA, 0);
Charles Keepax078e7182015-12-08 16:08:26 +00002553err_mutex:
2554 mutex_unlock(&dsp->pwr_lock);
2555
Mark Brown2159ad932012-10-11 11:54:02 +09002556 return ret;
2557}
2558EXPORT_SYMBOL_GPL(wm_adsp1_event);
2559
2560static int wm_adsp2_ena(struct wm_adsp *dsp)
2561{
2562 unsigned int val;
2563 int ret, count;
2564
Richard Fitzgeralde1ea1872017-04-05 11:07:59 +01002565 switch (dsp->rev) {
2566 case 0:
2567 ret = regmap_update_bits_async(dsp->regmap,
2568 dsp->base + ADSP2_CONTROL,
2569 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
2570 if (ret != 0)
2571 return ret;
2572 break;
2573 default:
2574 break;
2575 }
Mark Brown2159ad932012-10-11 11:54:02 +09002576
2577 /* Wait for the RAM to start, should be near instantaneous */
Charles Keepax939fd1e2013-12-18 09:25:49 +00002578 for (count = 0; count < 10; ++count) {
Charles Keepax7d00cd92016-02-19 14:44:43 +00002579 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val);
Mark Brown2159ad932012-10-11 11:54:02 +09002580 if (ret != 0)
2581 return ret;
Charles Keepax939fd1e2013-12-18 09:25:49 +00002582
2583 if (val & ADSP2_RAM_RDY)
2584 break;
2585
Charles Keepax1fa96f32016-09-26 10:15:22 +01002586 usleep_range(250, 500);
Charles Keepax939fd1e2013-12-18 09:25:49 +00002587 }
Mark Brown2159ad932012-10-11 11:54:02 +09002588
2589 if (!(val & ADSP2_RAM_RDY)) {
2590 adsp_err(dsp, "Failed to start DSP RAM\n");
2591 return -EBUSY;
2592 }
2593
2594 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
Mark Brown2159ad932012-10-11 11:54:02 +09002595
2596 return 0;
2597}
2598
Charles Keepax18b1a902014-01-09 09:06:54 +00002599static void wm_adsp2_boot_work(struct work_struct *work)
Charles Keepaxd8a64d62014-01-08 17:42:18 +00002600{
2601 struct wm_adsp *dsp = container_of(work,
2602 struct wm_adsp,
2603 boot_work);
2604 int ret;
Charles Keepaxd8a64d62014-01-08 17:42:18 +00002605
Charles Keepax078e7182015-12-08 16:08:26 +00002606 mutex_lock(&dsp->pwr_lock);
2607
Charles Keepax90d19ba2016-09-26 10:15:23 +01002608 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2609 ADSP2_MEM_ENA, ADSP2_MEM_ENA);
2610 if (ret != 0)
2611 goto err_mutex;
2612
Charles Keepaxd8a64d62014-01-08 17:42:18 +00002613 ret = wm_adsp2_ena(dsp);
2614 if (ret != 0)
Charles Keepaxd589d8b2017-01-24 11:44:01 +00002615 goto err_mem;
Charles Keepaxd8a64d62014-01-08 17:42:18 +00002616
2617 ret = wm_adsp_load(dsp);
2618 if (ret != 0)
Charles Keepax078e7182015-12-08 16:08:26 +00002619 goto err_ena;
Charles Keepaxd8a64d62014-01-08 17:42:18 +00002620
Charles Keepaxb618a1852015-04-13 13:27:53 +01002621 ret = wm_adsp2_setup_algs(dsp);
Charles Keepaxd8a64d62014-01-08 17:42:18 +00002622 if (ret != 0)
Charles Keepax078e7182015-12-08 16:08:26 +00002623 goto err_ena;
Charles Keepaxd8a64d62014-01-08 17:42:18 +00002624
2625 ret = wm_adsp_load_coeff(dsp);
2626 if (ret != 0)
Charles Keepax078e7182015-12-08 16:08:26 +00002627 goto err_ena;
Charles Keepaxd8a64d62014-01-08 17:42:18 +00002628
2629 /* Initialize caches for enabled and unset controls */
2630 ret = wm_coeff_init_control_caches(dsp);
2631 if (ret != 0)
Charles Keepax078e7182015-12-08 16:08:26 +00002632 goto err_ena;
Charles Keepaxd8a64d62014-01-08 17:42:18 +00002633
Richard Fitzgeralde1ea1872017-04-05 11:07:59 +01002634 switch (dsp->rev) {
2635 case 0:
2636 /* Turn DSP back off until we are ready to run */
2637 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2638 ADSP2_SYS_ENA, 0);
2639 if (ret != 0)
2640 goto err_ena;
2641 break;
2642 default:
2643 break;
2644 }
Charles Keepax90d19ba2016-09-26 10:15:23 +01002645
Charles Keepaxe7799742017-01-24 11:44:00 +00002646 dsp->booted = true;
2647
Charles Keepax078e7182015-12-08 16:08:26 +00002648 mutex_unlock(&dsp->pwr_lock);
2649
Charles Keepaxd8a64d62014-01-08 17:42:18 +00002650 return;
2651
Charles Keepax078e7182015-12-08 16:08:26 +00002652err_ena:
Charles Keepaxd8a64d62014-01-08 17:42:18 +00002653 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2654 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
Charles Keepaxd589d8b2017-01-24 11:44:01 +00002655err_mem:
2656 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2657 ADSP2_MEM_ENA, 0);
Charles Keepax078e7182015-12-08 16:08:26 +00002658err_mutex:
2659 mutex_unlock(&dsp->pwr_lock);
Charles Keepaxd8a64d62014-01-08 17:42:18 +00002660}
2661
Charles Keepaxd82d7672016-01-21 17:53:02 +00002662static void wm_adsp2_set_dspclk(struct wm_adsp *dsp, unsigned int freq)
2663{
2664 int ret;
2665
Richard Fitzgeralde1ea1872017-04-05 11:07:59 +01002666 switch (dsp->rev) {
2667 case 0:
2668 ret = regmap_update_bits_async(dsp->regmap,
2669 dsp->base + ADSP2_CLOCKING,
2670 ADSP2_CLK_SEL_MASK,
2671 freq << ADSP2_CLK_SEL_SHIFT);
2672 if (ret) {
2673 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
2674 return;
2675 }
2676 break;
2677 default:
2678 /* clock is handled by parent codec driver */
2679 break;
2680 }
Charles Keepaxd82d7672016-01-21 17:53:02 +00002681}
2682
Charles Keepaxaf813a62017-01-06 14:24:41 +00002683int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol,
2684 struct snd_ctl_elem_value *ucontrol)
2685{
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +00002686 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
Ajit Pandeyb1470d42018-08-07 18:30:42 +01002687 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
2688 struct soc_mixer_control *mc =
2689 (struct soc_mixer_control *)kcontrol->private_value;
2690 struct wm_adsp *dsp = &dsps[mc->shift - 1];
Charles Keepaxaf813a62017-01-06 14:24:41 +00002691
2692 ucontrol->value.integer.value[0] = dsp->preloaded;
2693
2694 return 0;
2695}
2696EXPORT_SYMBOL_GPL(wm_adsp2_preloader_get);
2697
2698int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol,
2699 struct snd_ctl_elem_value *ucontrol)
2700{
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +00002701 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
Ajit Pandeyb1470d42018-08-07 18:30:42 +01002702 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +00002703 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
Charles Keepaxaf813a62017-01-06 14:24:41 +00002704 struct soc_mixer_control *mc =
2705 (struct soc_mixer_control *)kcontrol->private_value;
Ajit Pandeyb1470d42018-08-07 18:30:42 +01002706 struct wm_adsp *dsp = &dsps[mc->shift - 1];
Charles Keepaxaf813a62017-01-06 14:24:41 +00002707 char preload[32];
2708
Richard Fitzgerald605391d2018-08-08 17:13:39 +01002709 snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name);
Charles Keepaxaf813a62017-01-06 14:24:41 +00002710
2711 dsp->preloaded = ucontrol->value.integer.value[0];
2712
2713 if (ucontrol->value.integer.value[0])
Charles Keepax95a594d2018-04-24 16:53:09 +01002714 snd_soc_component_force_enable_pin(component, preload);
Charles Keepaxaf813a62017-01-06 14:24:41 +00002715 else
Charles Keepax95a594d2018-04-24 16:53:09 +01002716 snd_soc_component_disable_pin(component, preload);
Charles Keepaxaf813a62017-01-06 14:24:41 +00002717
2718 snd_soc_dapm_sync(dapm);
2719
Stuart Henderson868e49a2018-07-19 11:50:37 +01002720 flush_work(&dsp->boot_work);
2721
Charles Keepaxaf813a62017-01-06 14:24:41 +00002722 return 0;
2723}
2724EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put);
2725
Mayuresh Kulkarni51a2c942017-04-05 11:08:00 +01002726static void wm_adsp_stop_watchdog(struct wm_adsp *dsp)
2727{
2728 switch (dsp->rev) {
2729 case 0:
2730 case 1:
2731 return;
2732 default:
2733 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG,
2734 ADSP2_WDT_ENA_MASK, 0);
2735 }
2736}
2737
Charles Keepax12db5ed2014-01-08 17:42:19 +00002738int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
Charles Keepaxd82d7672016-01-21 17:53:02 +00002739 struct snd_kcontrol *kcontrol, int event,
2740 unsigned int freq)
Charles Keepax12db5ed2014-01-08 17:42:19 +00002741{
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +00002742 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2743 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
Charles Keepax12db5ed2014-01-08 17:42:19 +00002744 struct wm_adsp *dsp = &dsps[w->shift];
Charles Keepax57a60cc2016-09-26 10:15:24 +01002745 struct wm_coeff_ctl *ctl;
Charles Keepax12db5ed2014-01-08 17:42:19 +00002746
Charles Keepax12db5ed2014-01-08 17:42:19 +00002747 switch (event) {
2748 case SND_SOC_DAPM_PRE_PMU:
Charles Keepaxd82d7672016-01-21 17:53:02 +00002749 wm_adsp2_set_dspclk(dsp, freq);
Charles Keepax12db5ed2014-01-08 17:42:19 +00002750 queue_work(system_unbound_wq, &dsp->boot_work);
2751 break;
Charles Keepax57a60cc2016-09-26 10:15:24 +01002752 case SND_SOC_DAPM_PRE_PMD:
Charles Keepaxbb24ee42017-01-24 11:43:59 +00002753 mutex_lock(&dsp->pwr_lock);
2754
Charles Keepax57a60cc2016-09-26 10:15:24 +01002755 wm_adsp_debugfs_clear(dsp);
2756
2757 dsp->fw_id = 0;
2758 dsp->fw_id_version = 0;
2759
2760 dsp->booted = false;
2761
2762 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2763 ADSP2_MEM_ENA, 0);
2764
2765 list_for_each_entry(ctl, &dsp->ctl_list, list)
2766 ctl->enabled = 0;
2767
2768 wm_adsp_free_alg_regions(dsp);
2769
Charles Keepaxbb24ee42017-01-24 11:43:59 +00002770 mutex_unlock(&dsp->pwr_lock);
2771
Charles Keepax57a60cc2016-09-26 10:15:24 +01002772 adsp_dbg(dsp, "Shutdown complete\n");
2773 break;
Charles Keepax12db5ed2014-01-08 17:42:19 +00002774 default:
2775 break;
Charles Keepaxcab272582014-04-17 13:42:54 +01002776 }
Charles Keepax12db5ed2014-01-08 17:42:19 +00002777
2778 return 0;
2779}
2780EXPORT_SYMBOL_GPL(wm_adsp2_early_event);
2781
Mark Brown2159ad932012-10-11 11:54:02 +09002782int wm_adsp2_event(struct snd_soc_dapm_widget *w,
2783 struct snd_kcontrol *kcontrol, int event)
2784{
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +00002785 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2786 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
Mark Brown2159ad932012-10-11 11:54:02 +09002787 struct wm_adsp *dsp = &dsps[w->shift];
2788 int ret;
2789
2790 switch (event) {
2791 case SND_SOC_DAPM_POST_PMU:
Charles Keepaxd8a64d62014-01-08 17:42:18 +00002792 flush_work(&dsp->boot_work);
Mark Browndd49e2c2012-12-02 21:50:46 +09002793
Charles Keepaxbb24ee42017-01-24 11:43:59 +00002794 mutex_lock(&dsp->pwr_lock);
2795
2796 if (!dsp->booted) {
2797 ret = -EIO;
2798 goto err;
2799 }
Mark Browndd49e2c2012-12-02 21:50:46 +09002800
Charles Keepax90d19ba2016-09-26 10:15:23 +01002801 ret = wm_adsp2_ena(dsp);
2802 if (ret != 0)
2803 goto err;
2804
Charles Keepaxcef45772016-09-20 13:52:33 +01002805 /* Sync set controls */
2806 ret = wm_coeff_sync_controls(dsp);
2807 if (ret != 0)
2808 goto err;
2809
Mayuresh Kulkarni51a2c942017-04-05 11:08:00 +01002810 wm_adsp2_lock(dsp, dsp->lock_regions);
2811
Charles Keepaxd8a64d62014-01-08 17:42:18 +00002812 ret = regmap_update_bits(dsp->regmap,
2813 dsp->base + ADSP2_CONTROL,
Charles Keepax00e4c3b2014-11-18 16:25:27 +00002814 ADSP2_CORE_ENA | ADSP2_START,
2815 ADSP2_CORE_ENA | ADSP2_START);
Mark Brown2159ad932012-10-11 11:54:02 +09002816 if (ret != 0)
2817 goto err;
Charles Keepax2cd19bd2015-12-15 11:29:46 +00002818
Charles Keepax48c2c992016-11-22 15:38:34 +00002819 if (wm_adsp_fw[dsp->fw].num_caps != 0) {
Charles Keepax2cd19bd2015-12-15 11:29:46 +00002820 ret = wm_adsp_buffer_init(dsp);
Charles Keepaxbb24ee42017-01-24 11:43:59 +00002821 if (ret < 0)
Charles Keepax48c2c992016-11-22 15:38:34 +00002822 goto err;
Charles Keepax48c2c992016-11-22 15:38:34 +00002823 }
Charles Keepax2cd19bd2015-12-15 11:29:46 +00002824
Charles Keepaxe7799742017-01-24 11:44:00 +00002825 dsp->running = true;
2826
Charles Keepax612047f2016-03-28 14:29:22 +01002827 mutex_unlock(&dsp->pwr_lock);
2828
Mark Brown2159ad932012-10-11 11:54:02 +09002829 break;
2830
2831 case SND_SOC_DAPM_PRE_PMD:
Richard Fitzgeraldf4f0c4c2016-11-09 17:14:17 +00002832 /* Tell the firmware to cleanup */
2833 wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN);
2834
Mayuresh Kulkarni51a2c942017-04-05 11:08:00 +01002835 wm_adsp_stop_watchdog(dsp);
2836
Richard Fitzgerald10337b02015-05-29 10:23:07 +01002837 /* Log firmware state, it can be useful for analysis */
Richard Fitzgeralde1ea1872017-04-05 11:07:59 +01002838 switch (dsp->rev) {
2839 case 0:
2840 wm_adsp2_show_fw_status(dsp);
2841 break;
2842 default:
2843 wm_adsp2v2_show_fw_status(dsp);
2844 break;
2845 }
Richard Fitzgerald10337b02015-05-29 10:23:07 +01002846
Charles Keepax078e7182015-12-08 16:08:26 +00002847 mutex_lock(&dsp->pwr_lock);
2848
Mark Brown1023dbd2013-01-11 22:58:28 +00002849 dsp->running = false;
2850
Richard Fitzgeralde1ea1872017-04-05 11:07:59 +01002851 regmap_update_bits(dsp->regmap,
2852 dsp->base + ADSP2_CONTROL,
Charles Keepax57a60cc2016-09-26 10:15:24 +01002853 ADSP2_CORE_ENA | ADSP2_START, 0);
Mark Brown973838a2012-11-28 17:20:32 +00002854
Mark Brown2d30b572013-01-28 20:18:17 +08002855 /* Make sure DMAs are quiesced */
Richard Fitzgeralde1ea1872017-04-05 11:07:59 +01002856 switch (dsp->rev) {
2857 case 0:
2858 regmap_write(dsp->regmap,
2859 dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2860 regmap_write(dsp->regmap,
2861 dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2862 regmap_write(dsp->regmap,
2863 dsp->base + ADSP2_WDMA_CONFIG_2, 0);
Simon Trimmer6facd2d2016-06-22 15:31:03 +01002864
Richard Fitzgeralde1ea1872017-04-05 11:07:59 +01002865 regmap_update_bits(dsp->regmap,
2866 dsp->base + ADSP2_CONTROL,
2867 ADSP2_SYS_ENA, 0);
2868 break;
2869 default:
2870 regmap_write(dsp->regmap,
2871 dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2872 regmap_write(dsp->regmap,
2873 dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2874 regmap_write(dsp->regmap,
2875 dsp->base + ADSP2V2_WDMA_CONFIG_2, 0);
2876 break;
2877 }
Mark Brown2d30b572013-01-28 20:18:17 +08002878
Charles Keepax2cd19bd2015-12-15 11:29:46 +00002879 if (wm_adsp_fw[dsp->fw].num_caps != 0)
2880 wm_adsp_buffer_free(dsp);
2881
Charles Keepax078e7182015-12-08 16:08:26 +00002882 mutex_unlock(&dsp->pwr_lock);
2883
Charles Keepax57a60cc2016-09-26 10:15:24 +01002884 adsp_dbg(dsp, "Execution stopped\n");
Mark Brown2159ad932012-10-11 11:54:02 +09002885 break;
2886
2887 default:
2888 break;
2889 }
2890
2891 return 0;
2892err:
2893 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
Mark Browna7f9be72012-11-28 19:53:59 +00002894 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
Charles Keepaxbb24ee42017-01-24 11:43:59 +00002895 mutex_unlock(&dsp->pwr_lock);
Mark Brown2159ad932012-10-11 11:54:02 +09002896 return ret;
2897}
2898EXPORT_SYMBOL_GPL(wm_adsp2_event);
Mark Brown973838a2012-11-28 17:20:32 +00002899
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +00002900int wm_adsp2_component_probe(struct wm_adsp *dsp, struct snd_soc_component *component)
Richard Fitzgeraldf5e2ce92015-06-11 11:32:30 +01002901{
Charles Keepaxaf813a62017-01-06 14:24:41 +00002902 char preload[32];
2903
Richard Fitzgerald605391d2018-08-08 17:13:39 +01002904 snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name);
Charles Keepax95a594d2018-04-24 16:53:09 +01002905 snd_soc_component_disable_pin(component, preload);
Richard Fitzgerald685f51a2016-11-22 16:58:57 +00002906
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +00002907 wm_adsp2_init_debugfs(dsp, component);
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +01002908
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +00002909 dsp->component = component;
Charles Keepaxaf813a62017-01-06 14:24:41 +00002910
Richard Fitzgerald0a047f02018-08-08 17:13:38 +01002911 return 0;
Richard Fitzgeraldf5e2ce92015-06-11 11:32:30 +01002912}
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +00002913EXPORT_SYMBOL_GPL(wm_adsp2_component_probe);
Richard Fitzgeraldf5e2ce92015-06-11 11:32:30 +01002914
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +00002915int wm_adsp2_component_remove(struct wm_adsp *dsp, struct snd_soc_component *component)
Richard Fitzgeraldf5e2ce92015-06-11 11:32:30 +01002916{
Richard Fitzgeraldf9f55e32015-06-11 11:32:32 +01002917 wm_adsp2_cleanup_debugfs(dsp);
2918
Richard Fitzgeraldf5e2ce92015-06-11 11:32:30 +01002919 return 0;
2920}
Kuninori Morimoto0fe1daa2018-02-13 02:03:12 +00002921EXPORT_SYMBOL_GPL(wm_adsp2_component_remove);
Richard Fitzgeraldf5e2ce92015-06-11 11:32:30 +01002922
Richard Fitzgerald81ac58b2015-06-02 11:53:34 +01002923int wm_adsp2_init(struct wm_adsp *dsp)
Mark Brown973838a2012-11-28 17:20:32 +00002924{
2925 int ret;
2926
Richard Fitzgeralddcad34f2018-11-12 13:36:39 +00002927 ret = wm_adsp_common_init(dsp);
Richard Fitzgerald605391d2018-08-08 17:13:39 +01002928 if (ret)
2929 return ret;
2930
Richard Fitzgeralde1ea1872017-04-05 11:07:59 +01002931 switch (dsp->rev) {
2932 case 0:
2933 /*
2934 * Disable the DSP memory by default when in reset for a small
2935 * power saving.
2936 */
2937 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2938 ADSP2_MEM_ENA, 0);
2939 if (ret) {
2940 adsp_err(dsp,
2941 "Failed to clear memory retention: %d\n", ret);
2942 return ret;
2943 }
2944 break;
2945 default:
2946 break;
Mark Brown10a2b662012-12-02 21:37:00 +09002947 }
2948
Charles Keepax3809f002015-04-13 13:27:54 +01002949 INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work);
Dimitris Papastamos6ab2b7b2013-05-08 14:15:35 +01002950
Mark Brown973838a2012-11-28 17:20:32 +00002951 return 0;
2952}
2953EXPORT_SYMBOL_GPL(wm_adsp2_init);
Praveen Diwakar0a37c6ef2014-07-04 11:17:41 +05302954
Richard Fitzgerald66225e92016-04-27 14:58:27 +01002955void wm_adsp2_remove(struct wm_adsp *dsp)
2956{
2957 struct wm_coeff_ctl *ctl;
2958
2959 while (!list_empty(&dsp->ctl_list)) {
2960 ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl,
2961 list);
2962 list_del(&ctl->list);
2963 wm_adsp_free_ctl_blk(ctl);
2964 }
2965}
2966EXPORT_SYMBOL_GPL(wm_adsp2_remove);
2967
Charles Keepaxedd71352016-05-04 17:11:55 +01002968static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr)
2969{
2970 return compr->buf != NULL;
2971}
2972
2973static int wm_adsp_compr_attach(struct wm_adsp_compr *compr)
2974{
2975 /*
2976 * Note this will be more complex once each DSP can support multiple
2977 * streams
2978 */
2979 if (!compr->dsp->buffer)
2980 return -EINVAL;
2981
2982 compr->buf = compr->dsp->buffer;
Charles Keepax721be3b2016-05-04 17:11:56 +01002983 compr->buf->compr = compr;
Charles Keepaxedd71352016-05-04 17:11:55 +01002984
2985 return 0;
2986}
2987
Charles Keepax721be3b2016-05-04 17:11:56 +01002988static void wm_adsp_compr_detach(struct wm_adsp_compr *compr)
2989{
2990 if (!compr)
2991 return;
2992
2993 /* Wake the poll so it can see buffer is no longer attached */
2994 if (compr->stream)
2995 snd_compr_fragment_elapsed(compr->stream);
2996
2997 if (wm_adsp_compr_attached(compr)) {
2998 compr->buf->compr = NULL;
2999 compr->buf = NULL;
3000 }
3001}
3002
Charles Keepax406abc92015-12-15 11:29:45 +00003003int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream)
3004{
3005 struct wm_adsp_compr *compr;
3006 int ret = 0;
3007
3008 mutex_lock(&dsp->pwr_lock);
3009
3010 if (wm_adsp_fw[dsp->fw].num_caps == 0) {
3011 adsp_err(dsp, "Firmware does not support compressed API\n");
3012 ret = -ENXIO;
3013 goto out;
3014 }
3015
3016 if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) {
3017 adsp_err(dsp, "Firmware does not support stream direction\n");
3018 ret = -EINVAL;
3019 goto out;
3020 }
3021
Charles Keepax95fe9592015-12-15 11:29:47 +00003022 if (dsp->compr) {
3023 /* It is expect this limitation will be removed in future */
3024 adsp_err(dsp, "Only a single stream supported per DSP\n");
3025 ret = -EBUSY;
3026 goto out;
3027 }
3028
Charles Keepax406abc92015-12-15 11:29:45 +00003029 compr = kzalloc(sizeof(*compr), GFP_KERNEL);
3030 if (!compr) {
3031 ret = -ENOMEM;
3032 goto out;
3033 }
3034
3035 compr->dsp = dsp;
3036 compr->stream = stream;
3037
3038 dsp->compr = compr;
3039
3040 stream->runtime->private_data = compr;
3041
3042out:
3043 mutex_unlock(&dsp->pwr_lock);
3044
3045 return ret;
3046}
3047EXPORT_SYMBOL_GPL(wm_adsp_compr_open);
3048
3049int wm_adsp_compr_free(struct snd_compr_stream *stream)
3050{
3051 struct wm_adsp_compr *compr = stream->runtime->private_data;
3052 struct wm_adsp *dsp = compr->dsp;
3053
3054 mutex_lock(&dsp->pwr_lock);
3055
Charles Keepax721be3b2016-05-04 17:11:56 +01003056 wm_adsp_compr_detach(compr);
Charles Keepax406abc92015-12-15 11:29:45 +00003057 dsp->compr = NULL;
3058
Charles Keepax83a40ce2016-01-06 12:33:19 +00003059 kfree(compr->raw_buf);
Charles Keepax406abc92015-12-15 11:29:45 +00003060 kfree(compr);
3061
3062 mutex_unlock(&dsp->pwr_lock);
3063
3064 return 0;
3065}
3066EXPORT_SYMBOL_GPL(wm_adsp_compr_free);
3067
3068static int wm_adsp_compr_check_params(struct snd_compr_stream *stream,
3069 struct snd_compr_params *params)
3070{
3071 struct wm_adsp_compr *compr = stream->runtime->private_data;
3072 struct wm_adsp *dsp = compr->dsp;
3073 const struct wm_adsp_fw_caps *caps;
3074 const struct snd_codec_desc *desc;
3075 int i, j;
3076
3077 if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE ||
3078 params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE ||
3079 params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS ||
3080 params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS ||
3081 params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) {
3082 adsp_err(dsp, "Invalid buffer fragsize=%d fragments=%d\n",
3083 params->buffer.fragment_size,
3084 params->buffer.fragments);
3085
3086 return -EINVAL;
3087 }
3088
3089 for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) {
3090 caps = &wm_adsp_fw[dsp->fw].caps[i];
3091 desc = &caps->desc;
3092
3093 if (caps->id != params->codec.id)
3094 continue;
3095
3096 if (stream->direction == SND_COMPRESS_PLAYBACK) {
3097 if (desc->max_ch < params->codec.ch_out)
3098 continue;
3099 } else {
3100 if (desc->max_ch < params->codec.ch_in)
3101 continue;
3102 }
3103
3104 if (!(desc->formats & (1 << params->codec.format)))
3105 continue;
3106
3107 for (j = 0; j < desc->num_sample_rates; ++j)
3108 if (desc->sample_rates[j] == params->codec.sample_rate)
3109 return 0;
3110 }
3111
3112 adsp_err(dsp, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n",
3113 params->codec.id, params->codec.ch_in, params->codec.ch_out,
3114 params->codec.sample_rate, params->codec.format);
3115 return -EINVAL;
3116}
3117
Charles Keepax565ace42016-01-06 12:33:18 +00003118static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr)
3119{
3120 return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE;
3121}
3122
Charles Keepax406abc92015-12-15 11:29:45 +00003123int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
3124 struct snd_compr_params *params)
3125{
3126 struct wm_adsp_compr *compr = stream->runtime->private_data;
Charles Keepax83a40ce2016-01-06 12:33:19 +00003127 unsigned int size;
Charles Keepax406abc92015-12-15 11:29:45 +00003128 int ret;
3129
3130 ret = wm_adsp_compr_check_params(stream, params);
3131 if (ret)
3132 return ret;
3133
3134 compr->size = params->buffer;
3135
3136 adsp_dbg(compr->dsp, "fragment_size=%d fragments=%d\n",
3137 compr->size.fragment_size, compr->size.fragments);
3138
Charles Keepax83a40ce2016-01-06 12:33:19 +00003139 size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf);
3140 compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL);
3141 if (!compr->raw_buf)
3142 return -ENOMEM;
3143
Charles Keepaxda2b3352016-02-02 16:41:36 +00003144 compr->sample_rate = params->codec.sample_rate;
3145
Charles Keepax406abc92015-12-15 11:29:45 +00003146 return 0;
3147}
3148EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params);
3149
3150int wm_adsp_compr_get_caps(struct snd_compr_stream *stream,
3151 struct snd_compr_caps *caps)
3152{
3153 struct wm_adsp_compr *compr = stream->runtime->private_data;
3154 int fw = compr->dsp->fw;
3155 int i;
3156
3157 if (wm_adsp_fw[fw].caps) {
3158 for (i = 0; i < wm_adsp_fw[fw].num_caps; i++)
3159 caps->codecs[i] = wm_adsp_fw[fw].caps[i].id;
3160
3161 caps->num_codecs = i;
3162 caps->direction = wm_adsp_fw[fw].compr_direction;
3163
3164 caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE;
3165 caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE;
3166 caps->min_fragments = WM_ADSP_MIN_FRAGMENTS;
3167 caps->max_fragments = WM_ADSP_MAX_FRAGMENTS;
3168 }
3169
3170 return 0;
3171}
3172EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps);
3173
Charles Keepax2cd19bd2015-12-15 11:29:46 +00003174static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type,
3175 unsigned int mem_addr,
3176 unsigned int num_words, u32 *data)
3177{
3178 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3179 unsigned int i, reg;
3180 int ret;
3181
3182 if (!mem)
3183 return -EINVAL;
3184
3185 reg = wm_adsp_region_to_reg(mem, mem_addr);
3186
3187 ret = regmap_raw_read(dsp->regmap, reg, data,
3188 sizeof(*data) * num_words);
3189 if (ret < 0)
3190 return ret;
3191
3192 for (i = 0; i < num_words; ++i)
3193 data[i] = be32_to_cpu(data[i]) & 0x00ffffffu;
3194
3195 return 0;
3196}
3197
3198static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type,
3199 unsigned int mem_addr, u32 *data)
3200{
3201 return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data);
3202}
3203
3204static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type,
3205 unsigned int mem_addr, u32 data)
3206{
3207 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3208 unsigned int reg;
3209
3210 if (!mem)
3211 return -EINVAL;
3212
3213 reg = wm_adsp_region_to_reg(mem, mem_addr);
3214
3215 data = cpu_to_be32(data & 0x00ffffffu);
3216
3217 return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data));
3218}
3219
3220static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf,
3221 unsigned int field_offset, u32 *data)
3222{
Andrew Fordfb13f192019-02-19 17:31:56 +00003223 return wm_adsp_read_data_word(buf->dsp, buf->host_buf_mem_type,
Charles Keepax2cd19bd2015-12-15 11:29:46 +00003224 buf->host_buf_ptr + field_offset, data);
3225}
3226
3227static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf,
3228 unsigned int field_offset, u32 data)
3229{
Andrew Fordfb13f192019-02-19 17:31:56 +00003230 return wm_adsp_write_data_word(buf->dsp, buf->host_buf_mem_type,
Charles Keepax2cd19bd2015-12-15 11:29:46 +00003231 buf->host_buf_ptr + field_offset, data);
3232}
3233
Richard Fitzgeraldd52ed4b2018-07-19 11:50:39 +01003234static int wm_adsp_legacy_host_buf_addr(struct wm_adsp_compr_buf *buf)
Charles Keepax2cd19bd2015-12-15 11:29:46 +00003235{
3236 struct wm_adsp_alg_region *alg_region;
3237 struct wm_adsp *dsp = buf->dsp;
3238 u32 xmalg, addr, magic;
3239 int i, ret;
3240
3241 alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id);
3242 xmalg = sizeof(struct wm_adsp_system_config_xm_hdr) / sizeof(__be32);
3243
3244 addr = alg_region->base + xmalg + ALG_XM_FIELD(magic);
3245 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic);
3246 if (ret < 0)
3247 return ret;
3248
3249 if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC)
3250 return -EINVAL;
3251
3252 addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr);
3253 for (i = 0; i < 5; ++i) {
3254 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr,
3255 &buf->host_buf_ptr);
3256 if (ret < 0)
3257 return ret;
3258
3259 if (buf->host_buf_ptr)
3260 break;
3261
3262 usleep_range(1000, 2000);
3263 }
3264
3265 if (!buf->host_buf_ptr)
3266 return -EIO;
3267
Andrew Fordfb13f192019-02-19 17:31:56 +00003268 buf->host_buf_mem_type = WMFW_ADSP2_XM;
3269
Charles Keepax2cd19bd2015-12-15 11:29:46 +00003270 adsp_dbg(dsp, "host_buf_ptr=%x\n", buf->host_buf_ptr);
3271
3272 return 0;
3273}
3274
Richard Fitzgeraldd52ed4b2018-07-19 11:50:39 +01003275static struct wm_coeff_ctl *
3276wm_adsp_find_host_buffer_ctrl(struct wm_adsp_compr_buf *buf)
3277{
3278 struct wm_adsp *dsp = buf->dsp;
3279 struct wm_coeff_ctl *ctl;
3280
3281 list_for_each_entry(ctl, &dsp->ctl_list, list) {
3282 if (ctl->type != WMFW_CTL_TYPE_HOST_BUFFER)
3283 continue;
3284
3285 if (!ctl->enabled)
3286 continue;
3287
Andrew Fordfb13f192019-02-19 17:31:56 +00003288 buf->host_buf_mem_type = ctl->alg_region.type;
Richard Fitzgeraldd52ed4b2018-07-19 11:50:39 +01003289 return ctl;
3290 }
3291
3292 return NULL;
3293}
3294
3295static int wm_adsp_buffer_locate(struct wm_adsp_compr_buf *buf)
3296{
3297 struct wm_adsp *dsp = buf->dsp;
3298 struct wm_coeff_ctl *ctl;
3299 unsigned int reg;
3300 u32 val;
3301 int i, ret;
3302
3303 ctl = wm_adsp_find_host_buffer_ctrl(buf);
3304 if (!ctl)
3305 return wm_adsp_legacy_host_buf_addr(buf);
3306
3307 ret = wm_coeff_base_reg(ctl, &reg);
3308 if (ret)
3309 return ret;
3310
3311 for (i = 0; i < 5; ++i) {
3312 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
3313 if (ret < 0)
3314 return ret;
3315
3316 if (val)
3317 break;
3318
3319 usleep_range(1000, 2000);
3320 }
3321
3322 if (!val)
3323 return -EIO;
3324
3325 buf->host_buf_ptr = be32_to_cpu(val);
3326 adsp_dbg(dsp, "host_buf_ptr=%x\n", buf->host_buf_ptr);
3327
3328 return 0;
3329}
3330
Charles Keepax2cd19bd2015-12-15 11:29:46 +00003331static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf)
3332{
3333 const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps;
3334 struct wm_adsp_buffer_region *region;
3335 u32 offset = 0;
3336 int i, ret;
3337
3338 for (i = 0; i < caps->num_regions; ++i) {
3339 region = &buf->regions[i];
3340
3341 region->offset = offset;
3342 region->mem_type = caps->region_defs[i].mem_type;
3343
3344 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset,
3345 &region->base_addr);
3346 if (ret < 0)
3347 return ret;
3348
3349 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset,
3350 &offset);
3351 if (ret < 0)
3352 return ret;
3353
3354 region->cumulative_size = offset;
3355
3356 adsp_dbg(buf->dsp,
Richard Fitzgeralde3a360b2018-10-19 13:25:16 +01003357 "region=%d type=%d base=%08x off=%08x size=%08x\n",
Charles Keepax2cd19bd2015-12-15 11:29:46 +00003358 i, region->mem_type, region->base_addr,
3359 region->offset, region->cumulative_size);
3360 }
3361
3362 return 0;
3363}
3364
Charles Keepax61fc0602018-02-26 10:49:47 +00003365static void wm_adsp_buffer_clear(struct wm_adsp_compr_buf *buf)
3366{
3367 buf->irq_count = 0xFFFFFFFF;
3368 buf->read_index = -1;
3369 buf->avail = 0;
3370}
3371
Charles Keepax2cd19bd2015-12-15 11:29:46 +00003372static int wm_adsp_buffer_init(struct wm_adsp *dsp)
3373{
3374 struct wm_adsp_compr_buf *buf;
3375 int ret;
3376
3377 buf = kzalloc(sizeof(*buf), GFP_KERNEL);
3378 if (!buf)
3379 return -ENOMEM;
3380
3381 buf->dsp = dsp;
Charles Keepax61fc0602018-02-26 10:49:47 +00003382
3383 wm_adsp_buffer_clear(buf);
Charles Keepax2cd19bd2015-12-15 11:29:46 +00003384
3385 ret = wm_adsp_buffer_locate(buf);
3386 if (ret < 0) {
3387 adsp_err(dsp, "Failed to acquire host buffer: %d\n", ret);
3388 goto err_buffer;
3389 }
3390
3391 buf->regions = kcalloc(wm_adsp_fw[dsp->fw].caps->num_regions,
3392 sizeof(*buf->regions), GFP_KERNEL);
3393 if (!buf->regions) {
3394 ret = -ENOMEM;
3395 goto err_buffer;
3396 }
3397
3398 ret = wm_adsp_buffer_populate(buf);
3399 if (ret < 0) {
3400 adsp_err(dsp, "Failed to populate host buffer: %d\n", ret);
3401 goto err_regions;
3402 }
3403
3404 dsp->buffer = buf;
3405
3406 return 0;
3407
3408err_regions:
3409 kfree(buf->regions);
3410err_buffer:
3411 kfree(buf);
3412 return ret;
3413}
3414
3415static int wm_adsp_buffer_free(struct wm_adsp *dsp)
3416{
3417 if (dsp->buffer) {
Charles Keepax721be3b2016-05-04 17:11:56 +01003418 wm_adsp_compr_detach(dsp->buffer->compr);
3419
Charles Keepax2cd19bd2015-12-15 11:29:46 +00003420 kfree(dsp->buffer->regions);
3421 kfree(dsp->buffer);
3422
3423 dsp->buffer = NULL;
3424 }
3425
3426 return 0;
3427}
3428
Charles Keepax95fe9592015-12-15 11:29:47 +00003429int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd)
3430{
3431 struct wm_adsp_compr *compr = stream->runtime->private_data;
3432 struct wm_adsp *dsp = compr->dsp;
3433 int ret = 0;
3434
3435 adsp_dbg(dsp, "Trigger: %d\n", cmd);
3436
3437 mutex_lock(&dsp->pwr_lock);
3438
3439 switch (cmd) {
3440 case SNDRV_PCM_TRIGGER_START:
Charles Keepax61fc0602018-02-26 10:49:47 +00003441 if (!wm_adsp_compr_attached(compr)) {
3442 ret = wm_adsp_compr_attach(compr);
3443 if (ret < 0) {
3444 adsp_err(dsp, "Failed to link buffer and stream: %d\n",
3445 ret);
3446 break;
3447 }
Charles Keepax95fe9592015-12-15 11:29:47 +00003448 }
Charles Keepax565ace42016-01-06 12:33:18 +00003449
Charles Keepax61fc0602018-02-26 10:49:47 +00003450 wm_adsp_buffer_clear(compr->buf);
3451
Charles Keepax565ace42016-01-06 12:33:18 +00003452 /* Trigger the IRQ at one fragment of data */
3453 ret = wm_adsp_buffer_write(compr->buf,
3454 HOST_BUFFER_FIELD(high_water_mark),
3455 wm_adsp_compr_frag_words(compr));
3456 if (ret < 0) {
3457 adsp_err(dsp, "Failed to set high water mark: %d\n",
3458 ret);
3459 break;
3460 }
Charles Keepax95fe9592015-12-15 11:29:47 +00003461 break;
3462 case SNDRV_PCM_TRIGGER_STOP:
3463 break;
3464 default:
3465 ret = -EINVAL;
3466 break;
3467 }
3468
3469 mutex_unlock(&dsp->pwr_lock);
3470
3471 return ret;
3472}
3473EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger);
3474
Charles Keepax565ace42016-01-06 12:33:18 +00003475static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf)
3476{
3477 int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1;
3478
3479 return buf->regions[last_region].cumulative_size;
3480}
3481
3482static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf)
3483{
3484 u32 next_read_index, next_write_index;
3485 int write_index, read_index, avail;
3486 int ret;
3487
3488 /* Only sync read index if we haven't already read a valid index */
3489 if (buf->read_index < 0) {
3490 ret = wm_adsp_buffer_read(buf,
3491 HOST_BUFFER_FIELD(next_read_index),
3492 &next_read_index);
3493 if (ret < 0)
3494 return ret;
3495
3496 read_index = sign_extend32(next_read_index, 23);
3497
3498 if (read_index < 0) {
3499 adsp_dbg(buf->dsp, "Avail check on unstarted stream\n");
3500 return 0;
3501 }
3502
3503 buf->read_index = read_index;
3504 }
3505
3506 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index),
3507 &next_write_index);
3508 if (ret < 0)
3509 return ret;
3510
3511 write_index = sign_extend32(next_write_index, 23);
3512
3513 avail = write_index - buf->read_index;
3514 if (avail < 0)
3515 avail += wm_adsp_buffer_size(buf);
3516
3517 adsp_dbg(buf->dsp, "readindex=0x%x, writeindex=0x%x, avail=%d\n",
Charles Keepax33d740e2016-03-28 14:29:21 +01003518 buf->read_index, write_index, avail * WM_ADSP_DATA_WORD_SIZE);
Charles Keepax565ace42016-01-06 12:33:18 +00003519
3520 buf->avail = avail;
3521
3522 return 0;
3523}
3524
Charles Keepax9771b182016-04-06 11:21:53 +01003525static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf *buf)
3526{
3527 int ret;
3528
3529 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error);
3530 if (ret < 0) {
3531 adsp_err(buf->dsp, "Failed to check buffer error: %d\n", ret);
3532 return ret;
3533 }
3534 if (buf->error != 0) {
3535 adsp_err(buf->dsp, "Buffer error occurred: %d\n", buf->error);
3536 return -EIO;
3537 }
3538
3539 return 0;
3540}
3541
Charles Keepax565ace42016-01-06 12:33:18 +00003542int wm_adsp_compr_handle_irq(struct wm_adsp *dsp)
3543{
Charles Keepax612047f2016-03-28 14:29:22 +01003544 struct wm_adsp_compr_buf *buf;
3545 struct wm_adsp_compr *compr;
Charles Keepax565ace42016-01-06 12:33:18 +00003546 int ret = 0;
3547
3548 mutex_lock(&dsp->pwr_lock);
3549
Charles Keepax612047f2016-03-28 14:29:22 +01003550 buf = dsp->buffer;
3551 compr = dsp->compr;
3552
Charles Keepax565ace42016-01-06 12:33:18 +00003553 if (!buf) {
Charles Keepax565ace42016-01-06 12:33:18 +00003554 ret = -ENODEV;
3555 goto out;
3556 }
3557
3558 adsp_dbg(dsp, "Handling buffer IRQ\n");
3559
Charles Keepax9771b182016-04-06 11:21:53 +01003560 ret = wm_adsp_buffer_get_error(buf);
3561 if (ret < 0)
Charles Keepax58476092016-04-06 11:21:54 +01003562 goto out_notify; /* Wake poll to report error */
Charles Keepax565ace42016-01-06 12:33:18 +00003563
3564 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count),
3565 &buf->irq_count);
3566 if (ret < 0) {
3567 adsp_err(dsp, "Failed to get irq_count: %d\n", ret);
3568 goto out;
3569 }
3570
3571 ret = wm_adsp_buffer_update_avail(buf);
3572 if (ret < 0) {
3573 adsp_err(dsp, "Error reading avail: %d\n", ret);
3574 goto out;
3575 }
3576
Charles Keepax20b7f7c2016-05-13 16:45:17 +01003577 if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2)
3578 ret = WM_ADSP_COMPR_VOICE_TRIGGER;
3579
Charles Keepax58476092016-04-06 11:21:54 +01003580out_notify:
Charles Keepaxc7dae7c2016-02-19 14:44:41 +00003581 if (compr && compr->stream)
Charles Keepax83a40ce2016-01-06 12:33:19 +00003582 snd_compr_fragment_elapsed(compr->stream);
3583
Charles Keepax565ace42016-01-06 12:33:18 +00003584out:
3585 mutex_unlock(&dsp->pwr_lock);
3586
3587 return ret;
3588}
3589EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq);
3590
3591static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf)
3592{
3593 if (buf->irq_count & 0x01)
3594 return 0;
3595
3596 adsp_dbg(buf->dsp, "Enable IRQ(0x%x) for next fragment\n",
3597 buf->irq_count);
3598
3599 buf->irq_count |= 0x01;
3600
3601 return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack),
3602 buf->irq_count);
3603}
3604
3605int wm_adsp_compr_pointer(struct snd_compr_stream *stream,
3606 struct snd_compr_tstamp *tstamp)
3607{
3608 struct wm_adsp_compr *compr = stream->runtime->private_data;
Charles Keepax565ace42016-01-06 12:33:18 +00003609 struct wm_adsp *dsp = compr->dsp;
Charles Keepax612047f2016-03-28 14:29:22 +01003610 struct wm_adsp_compr_buf *buf;
Charles Keepax565ace42016-01-06 12:33:18 +00003611 int ret = 0;
3612
3613 adsp_dbg(dsp, "Pointer request\n");
3614
3615 mutex_lock(&dsp->pwr_lock);
3616
Charles Keepax612047f2016-03-28 14:29:22 +01003617 buf = compr->buf;
3618
Charles Keepax28ee3d72016-06-13 14:17:12 +01003619 if (!compr->buf || compr->buf->error) {
Charles Keepax8d280662016-06-13 14:17:11 +01003620 snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN);
Charles Keepax565ace42016-01-06 12:33:18 +00003621 ret = -EIO;
3622 goto out;
3623 }
3624
3625 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
3626 ret = wm_adsp_buffer_update_avail(buf);
3627 if (ret < 0) {
3628 adsp_err(dsp, "Error reading avail: %d\n", ret);
3629 goto out;
3630 }
3631
3632 /*
3633 * If we really have less than 1 fragment available tell the
3634 * DSP to inform us once a whole fragment is available.
3635 */
3636 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
Charles Keepax58476092016-04-06 11:21:54 +01003637 ret = wm_adsp_buffer_get_error(buf);
Charles Keepax8d280662016-06-13 14:17:11 +01003638 if (ret < 0) {
3639 if (compr->buf->error)
3640 snd_compr_stop_error(stream,
3641 SNDRV_PCM_STATE_XRUN);
Charles Keepax58476092016-04-06 11:21:54 +01003642 goto out;
Charles Keepax8d280662016-06-13 14:17:11 +01003643 }
Charles Keepax58476092016-04-06 11:21:54 +01003644
Charles Keepax565ace42016-01-06 12:33:18 +00003645 ret = wm_adsp_buffer_reenable_irq(buf);
3646 if (ret < 0) {
3647 adsp_err(dsp,
3648 "Failed to re-enable buffer IRQ: %d\n",
3649 ret);
3650 goto out;
3651 }
3652 }
3653 }
3654
3655 tstamp->copied_total = compr->copied_total;
3656 tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE;
Charles Keepaxda2b3352016-02-02 16:41:36 +00003657 tstamp->sampling_rate = compr->sample_rate;
Charles Keepax565ace42016-01-06 12:33:18 +00003658
3659out:
3660 mutex_unlock(&dsp->pwr_lock);
3661
3662 return ret;
3663}
3664EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer);
3665
Charles Keepax83a40ce2016-01-06 12:33:19 +00003666static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target)
3667{
3668 struct wm_adsp_compr_buf *buf = compr->buf;
3669 u8 *pack_in = (u8 *)compr->raw_buf;
3670 u8 *pack_out = (u8 *)compr->raw_buf;
3671 unsigned int adsp_addr;
3672 int mem_type, nwords, max_read;
3673 int i, j, ret;
3674
3675 /* Calculate read parameters */
3676 for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i)
3677 if (buf->read_index < buf->regions[i].cumulative_size)
3678 break;
3679
3680 if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions)
3681 return -EINVAL;
3682
3683 mem_type = buf->regions[i].mem_type;
3684 adsp_addr = buf->regions[i].base_addr +
3685 (buf->read_index - buf->regions[i].offset);
3686
3687 max_read = wm_adsp_compr_frag_words(compr);
3688 nwords = buf->regions[i].cumulative_size - buf->read_index;
3689
3690 if (nwords > target)
3691 nwords = target;
3692 if (nwords > buf->avail)
3693 nwords = buf->avail;
3694 if (nwords > max_read)
3695 nwords = max_read;
3696 if (!nwords)
3697 return 0;
3698
3699 /* Read data from DSP */
3700 ret = wm_adsp_read_data_block(buf->dsp, mem_type, adsp_addr,
3701 nwords, compr->raw_buf);
3702 if (ret < 0)
3703 return ret;
3704
3705 /* Remove the padding bytes from the data read from the DSP */
3706 for (i = 0; i < nwords; i++) {
3707 for (j = 0; j < WM_ADSP_DATA_WORD_SIZE; j++)
3708 *pack_out++ = *pack_in++;
3709
3710 pack_in += sizeof(*(compr->raw_buf)) - WM_ADSP_DATA_WORD_SIZE;
3711 }
3712
3713 /* update read index to account for words read */
3714 buf->read_index += nwords;
3715 if (buf->read_index == wm_adsp_buffer_size(buf))
3716 buf->read_index = 0;
3717
3718 ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index),
3719 buf->read_index);
3720 if (ret < 0)
3721 return ret;
3722
3723 /* update avail to account for words read */
3724 buf->avail -= nwords;
3725
3726 return nwords;
3727}
3728
3729static int wm_adsp_compr_read(struct wm_adsp_compr *compr,
3730 char __user *buf, size_t count)
3731{
3732 struct wm_adsp *dsp = compr->dsp;
3733 int ntotal = 0;
3734 int nwords, nbytes;
3735
3736 adsp_dbg(dsp, "Requested read of %zu bytes\n", count);
3737
Charles Keepax28ee3d72016-06-13 14:17:12 +01003738 if (!compr->buf || compr->buf->error) {
Charles Keepax8d280662016-06-13 14:17:11 +01003739 snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN);
Charles Keepax83a40ce2016-01-06 12:33:19 +00003740 return -EIO;
Charles Keepax8d280662016-06-13 14:17:11 +01003741 }
Charles Keepax83a40ce2016-01-06 12:33:19 +00003742
3743 count /= WM_ADSP_DATA_WORD_SIZE;
3744
3745 do {
3746 nwords = wm_adsp_buffer_capture_block(compr, count);
3747 if (nwords < 0) {
3748 adsp_err(dsp, "Failed to capture block: %d\n", nwords);
3749 return nwords;
3750 }
3751
3752 nbytes = nwords * WM_ADSP_DATA_WORD_SIZE;
3753
3754 adsp_dbg(dsp, "Read %d bytes\n", nbytes);
3755
3756 if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) {
3757 adsp_err(dsp, "Failed to copy data to user: %d, %d\n",
3758 ntotal, nbytes);
3759 return -EFAULT;
3760 }
3761
3762 count -= nwords;
3763 ntotal += nbytes;
3764 } while (nwords > 0 && count > 0);
3765
3766 compr->copied_total += ntotal;
3767
3768 return ntotal;
3769}
3770
3771int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf,
3772 size_t count)
3773{
3774 struct wm_adsp_compr *compr = stream->runtime->private_data;
3775 struct wm_adsp *dsp = compr->dsp;
3776 int ret;
3777
3778 mutex_lock(&dsp->pwr_lock);
3779
3780 if (stream->direction == SND_COMPRESS_CAPTURE)
3781 ret = wm_adsp_compr_read(compr, buf, count);
3782 else
3783 ret = -ENOTSUPP;
3784
3785 mutex_unlock(&dsp->pwr_lock);
3786
3787 return ret;
3788}
3789EXPORT_SYMBOL_GPL(wm_adsp_compr_copy);
3790
Mayuresh Kulkarni51a2c942017-04-05 11:08:00 +01003791int wm_adsp2_lock(struct wm_adsp *dsp, unsigned int lock_regions)
3792{
3793 struct regmap *regmap = dsp->regmap;
3794 unsigned int code0, code1, lock_reg;
3795
3796 if (!(lock_regions & WM_ADSP2_REGION_ALL))
3797 return 0;
3798
3799 lock_regions &= WM_ADSP2_REGION_ALL;
3800 lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0;
3801
3802 while (lock_regions) {
3803 code0 = code1 = 0;
3804 if (lock_regions & BIT(0)) {
3805 code0 = ADSP2_LOCK_CODE_0;
3806 code1 = ADSP2_LOCK_CODE_1;
3807 }
3808 if (lock_regions & BIT(1)) {
3809 code0 |= ADSP2_LOCK_CODE_0 << ADSP2_LOCK_REGION_SHIFT;
3810 code1 |= ADSP2_LOCK_CODE_1 << ADSP2_LOCK_REGION_SHIFT;
3811 }
3812 regmap_write(regmap, lock_reg, code0);
3813 regmap_write(regmap, lock_reg, code1);
3814 lock_regions >>= 2;
3815 lock_reg += 2;
3816 }
3817
3818 return 0;
3819}
3820EXPORT_SYMBOL_GPL(wm_adsp2_lock);
3821
3822irqreturn_t wm_adsp2_bus_error(struct wm_adsp *dsp)
3823{
3824 unsigned int val;
3825 struct regmap *regmap = dsp->regmap;
3826 int ret = 0;
3827
3828 ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val);
3829 if (ret) {
3830 adsp_err(dsp,
3831 "Failed to read Region Lock Ctrl register: %d\n", ret);
3832 return IRQ_HANDLED;
3833 }
3834
3835 if (val & ADSP2_WDT_TIMEOUT_STS_MASK) {
3836 adsp_err(dsp, "watchdog timeout error\n");
3837 wm_adsp_stop_watchdog(dsp);
3838 }
3839
3840 if (val & (ADSP2_SLAVE_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) {
3841 if (val & ADSP2_SLAVE_ERR_MASK)
3842 adsp_err(dsp, "bus error: slave error\n");
3843 else
3844 adsp_err(dsp, "bus error: region lock error\n");
3845
3846 ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val);
3847 if (ret) {
3848 adsp_err(dsp,
3849 "Failed to read Bus Err Addr register: %d\n",
3850 ret);
3851 return IRQ_HANDLED;
3852 }
3853
3854 adsp_err(dsp, "bus error address = 0x%x\n",
3855 val & ADSP2_BUS_ERR_ADDR_MASK);
3856
3857 ret = regmap_read(regmap,
3858 dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR,
3859 &val);
3860 if (ret) {
3861 adsp_err(dsp,
3862 "Failed to read Pmem Xmem Err Addr register: %d\n",
3863 ret);
3864 return IRQ_HANDLED;
3865 }
3866
3867 adsp_err(dsp, "xmem error address = 0x%x\n",
3868 val & ADSP2_XMEM_ERR_ADDR_MASK);
3869 adsp_err(dsp, "pmem error address = 0x%x\n",
3870 (val & ADSP2_PMEM_ERR_ADDR_MASK) >>
3871 ADSP2_PMEM_ERR_ADDR_SHIFT);
3872 }
3873
3874 regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL,
3875 ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT);
3876
3877 return IRQ_HANDLED;
3878}
3879EXPORT_SYMBOL_GPL(wm_adsp2_bus_error);
3880
Praveen Diwakar0a37c6ef2014-07-04 11:17:41 +05303881MODULE_LICENSE("GPL v2");