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chuangcheng peng021cfea2023-09-12 18:37:42 +08001/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
Chuanzhi Wang670fc042020-08-12 11:11:04 +08002/*
3 * dmx.h
4 *
5 * Copyright (C) 2000 Marcus Metzler <marcus@convergence.de>
6 * & Ralph Metzler <ralph@convergence.de>
7 * for convergence integrated media GmbH
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public License
11 * as published by the Free Software Foundation; either version 2.1
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU Lesser General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 *
23 */
24
25#ifndef _UAPI_DVBDMX_H_
26#define _UAPI_DVBDMX_H_
27
28#include <linux/types.h>
29#include <asm/ioctl.h>
30#ifndef __KERNEL__
31#include <time.h>
32#endif
33
34#define CONFIG_AMLOGIC_DVB_COMPAT
35#define DMX_FILTER_SIZE 16
36
chuangcheng peng021cfea2023-09-12 18:37:42 +080037/**
38 * enum dmx_output - Output for the demux.
39 *
40 * @DMX_OUT_DECODER:
41 * Streaming directly to decoder.
42 * @DMX_OUT_TAP:
43 * Output going to a memory buffer (to be retrieved via the read command).
44 * Delivers the stream output to the demux device on which the ioctl
45 * is called.
46 * @DMX_OUT_TS_TAP:
47 * Output multiplexed into a new TS (to be retrieved by reading from the
48 * logical DVR device). Routes output to the logical DVR device
49 * ``/dev/dvb/adapter?/dvr?``, which delivers a TS multiplexed from all
50 * filters for which @DMX_OUT_TS_TAP was specified.
51 * @DMX_OUT_TSDEMUX_TAP:
52 * Like @DMX_OUT_TS_TAP but retrieved from the DMX device.
53 */
54enum dmx_output {
55 DMX_OUT_DECODER,
56 DMX_OUT_TAP,
57 DMX_OUT_TS_TAP,
58 DMX_OUT_TSDEMUX_TAP
Chuanzhi Wang670fc042020-08-12 11:11:04 +080059};
60
Chuanzhi Wang670fc042020-08-12 11:11:04 +080061
chuangcheng peng021cfea2023-09-12 18:37:42 +080062/**
63 * enum dmx_input - Input from the demux.
64 *
65 * @DMX_IN_FRONTEND: Input from a front-end device.
66 * @DMX_IN_DVR: Input from the logical DVR device.
67 */
68enum dmx_input {
69 DMX_IN_FRONTEND,
70 DMX_IN_DVR
71};
Chuanzhi Wang670fc042020-08-12 11:11:04 +080072
chuangcheng peng021cfea2023-09-12 18:37:42 +080073/**
74 * enum dmx_ts_pes - type of the PES filter.
75 *
76 * @DMX_PES_AUDIO0: first audio PID. Also referred as @DMX_PES_AUDIO.
77 * @DMX_PES_VIDEO0: first video PID. Also referred as @DMX_PES_VIDEO.
78 * @DMX_PES_TELETEXT0: first teletext PID. Also referred as @DMX_PES_TELETEXT.
79 * @DMX_PES_SUBTITLE0: first subtitle PID. Also referred as @DMX_PES_SUBTITLE.
80 * @DMX_PES_PCR0: first Program Clock Reference PID.
81 * Also referred as @DMX_PES_PCR.
82 *
83 * @DMX_PES_AUDIO1: second audio PID.
84 * @DMX_PES_VIDEO1: second video PID.
85 * @DMX_PES_TELETEXT1: second teletext PID.
86 * @DMX_PES_SUBTITLE1: second subtitle PID.
87 * @DMX_PES_PCR1: second Program Clock Reference PID.
88 *
89 * @DMX_PES_AUDIO2: third audio PID.
90 * @DMX_PES_VIDEO2: third video PID.
91 * @DMX_PES_TELETEXT2: third teletext PID.
92 * @DMX_PES_SUBTITLE2: third subtitle PID.
93 * @DMX_PES_PCR2: third Program Clock Reference PID.
94 *
95 * @DMX_PES_AUDIO3: fourth audio PID.
96 * @DMX_PES_VIDEO3: fourth video PID.
97 * @DMX_PES_TELETEXT3: fourth teletext PID.
98 * @DMX_PES_SUBTITLE3: fourth subtitle PID.
99 * @DMX_PES_PCR3: fourth Program Clock Reference PID.
100 *
101 * @DMX_PES_OTHER: any other PID.
102 */
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800103
chuangcheng peng021cfea2023-09-12 18:37:42 +0800104enum dmx_ts_pes {
105 DMX_PES_AUDIO0,
106 DMX_PES_VIDEO0,
107 DMX_PES_TELETEXT0,
108 DMX_PES_SUBTITLE0,
109 DMX_PES_PCR0,
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800110
chuangcheng peng021cfea2023-09-12 18:37:42 +0800111 DMX_PES_AUDIO1,
112 DMX_PES_VIDEO1,
113 DMX_PES_TELETEXT1,
114 DMX_PES_SUBTITLE1,
115 DMX_PES_PCR1,
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800116
chuangcheng peng021cfea2023-09-12 18:37:42 +0800117 DMX_PES_AUDIO2,
118 DMX_PES_VIDEO2,
119 DMX_PES_TELETEXT2,
120 DMX_PES_SUBTITLE2,
121 DMX_PES_PCR2,
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800122
chuangcheng peng021cfea2023-09-12 18:37:42 +0800123 DMX_PES_AUDIO3,
124 DMX_PES_VIDEO3,
125 DMX_PES_TELETEXT3,
126 DMX_PES_SUBTITLE3,
127 DMX_PES_PCR3,
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800128
chuangcheng peng021cfea2023-09-12 18:37:42 +0800129 DMX_PES_OTHER
130};
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800131
132#define DMX_PES_AUDIO DMX_PES_AUDIO0
133#define DMX_PES_VIDEO DMX_PES_VIDEO0
134#define DMX_PES_TELETEXT DMX_PES_TELETEXT0
135#define DMX_PES_SUBTITLE DMX_PES_SUBTITLE0
136#define DMX_PES_PCR DMX_PES_PCR0
137
138
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800139
chuangcheng peng021cfea2023-09-12 18:37:42 +0800140/**
141 * struct dmx_filter - Specifies a section header filter.
142 *
143 * @filter: bit array with bits to be matched at the section header.
144 * @mask: bits that are valid at the filter bit array.
145 * @mode: mode of match: if bit is zero, it will match if equal (positive
146 * match); if bit is one, it will match if the bit is negated.
147 *
148 * Note: All arrays in this struct have a size of DMX_FILTER_SIZE (16 bytes).
149 */
150struct dmx_filter {
151 __u8 filter[DMX_FILTER_SIZE];
152 __u8 mask[DMX_FILTER_SIZE];
153 __u8 mode[DMX_FILTER_SIZE];
154};
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800155
chuangcheng peng021cfea2023-09-12 18:37:42 +0800156/**
157 * struct dmx_sct_filter_params - Specifies a section filter.
158 *
159 * @pid: PID to be filtered.
160 * @filter: section header filter, as defined by &struct dmx_filter.
161 * @timeout: maximum time to filter, in milliseconds.
162 * @flags: extra flags for the section filter.
163 *
164 * Carries the configuration for a MPEG-TS section filter.
165 *
166 * The @flags can be:
167 *
168 * - %DMX_CHECK_CRC - only deliver sections where the CRC check succeeded;
169 * - %DMX_ONESHOT - disable the section filter after one section
170 * has been delivered;
171 * - %DMX_IMMEDIATE_START - Start filter immediately without requiring a
172 * :ref:`DMX_START`.
173 */
174struct dmx_sct_filter_params {
175 __u16 pid;
176 struct dmx_filter filter;
177 __u32 timeout;
178 __u32 flags;
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800179#define DMX_CHECK_CRC 1
180#define DMX_ONESHOT 2
181#define DMX_IMMEDIATE_START 4
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800182#ifdef CONFIG_AMLOGIC_DVB_COMPAT
183#define DMX_USE_SWFILTER 0x100
Yahui Hance15e9c2020-12-08 18:08:32 +0800184
185/*bit 8~15 for mem sec_level*/
186#define DMX_MEM_SEC_LEVEL1 (1 << 10)
Wentao MAa2889f62023-01-31 13:39:31 +0800187#define DMX_MEM_SEC_LEVEL2 (2 << 10)
188#define DMX_MEM_SEC_LEVEL3 (3 << 10)
189#define DMX_MEM_SEC_LEVEL4 (4 << 10)
190#define DMX_MEM_SEC_LEVEL5 (5 << 10)
191#define DMX_MEM_SEC_LEVEL6 (6 << 10)
192#define DMX_MEM_SEC_LEVEL7 (7 << 10)
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800193#endif
194};
195
196#ifdef CONFIG_AMLOGIC_DVB_COMPAT
197
198enum dmx_input_source {
chuangcheng peng021cfea2023-09-12 18:37:42 +0800199 INPUT_DEMOD,
200 INPUT_LOCAL,
201 INPUT_LOCAL_SEC
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800202};
203
204/**
205 * struct dmx_non_sec_es_header - non-sec Elementary Stream (ES) Header
206 *
chuangcheng peng021cfea2023-09-12 18:37:42 +0800207 * @pts_dts_flag:[1:0], 10:pts valid, 01:dts valid
208 * @pts_dts_flag:[3:2], 10:scb is scrambled, 01:pscp invalid
209 * @pts: pts value
210 * @dts: dts value
211 * @len: data len
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800212 */
213struct dmx_non_sec_es_header {
chuangcheng peng021cfea2023-09-12 18:37:42 +0800214 __u8 pts_dts_flag;
215 __u64 pts;
216 __u64 dts;
217 __u32 len;
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800218};
219
220/**
221 * struct dmx_sec_es_data - sec Elementary Stream (ES)
222 *
chuangcheng peng021cfea2023-09-12 18:37:42 +0800223 * @pts_dts_flag:[1:0], 10:pts valid, 01:dts valid
224 * @pts_dts_flag:[3:2], 10:scb is scrambled, 01:pscp invalid
225 * @pts: pts value
226 * @dts: dts value
227 * @buf_start: buf start addr
228 * @buf_end: buf end addr
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800229 * @data_start: data start addr
230 * @data_end: data end addr
231 */
232struct dmx_sec_es_data {
chuangcheng peng021cfea2023-09-12 18:37:42 +0800233 __u8 pts_dts_flag;
234 __u64 pts;
235 __u64 dts;
236 __u32 buf_start;
237 __u32 buf_end;
238 __u32 data_start;
239 __u32 data_end;
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800240};
241
hualing chenf9867402020-09-23 17:06:20 +0800242struct dmx_sec_ts_data {
chuangcheng peng021cfea2023-09-12 18:37:42 +0800243 __u32 buf_start;
244 __u32 buf_end;
245 __u32 data_start;
246 __u32 data_end;
247};
248
249struct dmx_temi_data {
250 __u8 pts_dts_flag;
251 __u64 pts;
252 __u64 dts;
253 __u8 temi[188];
hualing chenf9867402020-09-23 17:06:20 +0800254};
255
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800256enum dmx_audio_format {
chuangcheng peng021cfea2023-09-12 18:37:42 +0800257 AUDIO_UNKNOWN = 0, /* unknown media */
258 AUDIO_MPX = 1, /* mpeg audio MP2/MP3 */
259 AUDIO_AC3 = 2, /* Dolby AC3/EAC3 */
260 AUDIO_AAC_ADTS = 3, /* AAC-ADTS */
261 AUDIO_AAC_LOAS = 4, /* AAC-LOAS */
262 AUDIO_DTS = 5, /* DTS */
263 AUDIO_MAX
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800264};
265
266struct dmx_mem_info {
chuangcheng peng021cfea2023-09-12 18:37:42 +0800267 __u32 dmx_total_size;
268 __u32 dmx_buf_phy_start;
269 __u32 dmx_free_size;
270 __u32 dvb_core_total_size;
271 __u32 dvb_core_free_size;
272 __u32 wp_offset;
273 __u64 newest_pts;
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800274};
275
hualing chenf9867402020-09-23 17:06:20 +0800276struct dmx_sec_mem {
chuangcheng peng021cfea2023-09-12 18:37:42 +0800277 __u32 buff;
278 __u32 size;
hualing chenf9867402020-09-23 17:06:20 +0800279};
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800280#endif
281
282/**
283 * struct dmx_pes_filter_params - Specifies Packetized Elementary Stream (PES)
chuangcheng peng021cfea2023-09-12 18:37:42 +0800284 * filter parameters.
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800285 *
chuangcheng peng021cfea2023-09-12 18:37:42 +0800286 * @pid: PID to be filtered.
287 * @input: Demux input, as specified by &enum dmx_input.
288 * @output: Demux output, as specified by &enum dmx_output.
289 * @pes_type: Type of the pes filter, as specified by &enum dmx_pes_type.
290 * @flags: Demux PES flags.
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800291 */
292struct dmx_pes_filter_params {
chuangcheng peng021cfea2023-09-12 18:37:42 +0800293 __u16 pid;
294 enum dmx_input input;
295 enum dmx_output output;
296 enum dmx_ts_pes pes_type;
297 __u32 flags;
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800298#ifdef CONFIG_AMLOGIC_DVB_COMPAT
299/*bit 8~15 for mem sec_level*/
300#define DMX_MEM_SEC_LEVEL1 (1 << 10)
Wentao MAa2889f62023-01-31 13:39:31 +0800301#define DMX_MEM_SEC_LEVEL2 (2 << 10)
302#define DMX_MEM_SEC_LEVEL3 (3 << 10)
303#define DMX_MEM_SEC_LEVEL4 (4 << 10)
304#define DMX_MEM_SEC_LEVEL5 (5 << 10)
305#define DMX_MEM_SEC_LEVEL6 (6 << 10)
306#define DMX_MEM_SEC_LEVEL7 (7 << 10)
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800307
308/*bit 16~23 for output */
309#define DMX_ES_OUTPUT (1 << 16)
310/*set raw mode, it will send the struct dmx_sec_es_data, not es data*/
chuangcheng peng021cfea2023-09-12 18:37:42 +0800311#define DMX_OUTPUT_RAW_MODE (1 << 17)
312#define DMX_TEMI_FLAGS (1 << 18)
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800313
314/*24~31 one byte for audio type, dmx_audio_format_t*/
315#define DMX_AUDIO_FORMAT_BIT 24
316
317#endif
318};
319
320typedef struct dmx_caps {
hualing chen002e5b92022-02-23 17:51:21 +0800321 __u32 caps;
322 int num_decoders;
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800323} dmx_caps_t;
324
325typedef enum dmx_source {
hualing chen002e5b92022-02-23 17:51:21 +0800326 DMX_SOURCE_FRONT0 = 0,
327 DMX_SOURCE_FRONT1,
328 DMX_SOURCE_FRONT2,
329 DMX_SOURCE_FRONT3,
330 DMX_SOURCE_DVR0 = 16,
331 DMX_SOURCE_DVR1,
332 DMX_SOURCE_DVR2,
333 DMX_SOURCE_DVR3,
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800334
335#ifdef CONFIG_AMLOGIC_DVB_COMPAT
hualing chen002e5b92022-02-23 17:51:21 +0800336 DMX_SOURCE_FRONT0_OFFSET = 100,
337 DMX_SOURCE_FRONT1_OFFSET,
338 DMX_SOURCE_FRONT2_OFFSET
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800339#endif
340} dmx_source_t;
341
chuangcheng peng021cfea2023-09-12 18:37:42 +0800342/**
343 * struct dmx_stc - Stores System Time Counter (STC) information.
344 *
345 * @num: input data: number of the STC, from 0 to N.
346 * @base: output: divisor for STC to get 90 kHz clock.
347 * @stc: output: stc in @base * 90 kHz units.
348 */
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800349struct dmx_stc {
chuangcheng peng021cfea2023-09-12 18:37:42 +0800350 unsigned int num;
351 unsigned int base;
352 __u64 stc;
353};
354
355/**
356 * enum dmx_buffer_flags - DMX memory-mapped buffer flags
357 *
358 * @DMX_BUFFER_FLAG_HAD_CRC32_DISCARD:
359 * Indicates that the Kernel discarded one or more frames due to wrong
360 * CRC32 checksum.
361 * @DMX_BUFFER_FLAG_TEI:
362 * Indicates that the Kernel has detected a Transport Error indicator
363 * (TEI) on a filtered pid.
364 * @DMX_BUFFER_PKT_COUNTER_MISMATCH:
365 * Indicates that the Kernel has detected a packet counter mismatch
366 * on a filtered pid.
367 * @DMX_BUFFER_FLAG_DISCONTINUITY_DETECTED:
368 * Indicates that the Kernel has detected one or more frame discontinuity.
369 * @DMX_BUFFER_FLAG_DISCONTINUITY_INDICATOR:
370 * Received at least one packet with a frame discontinuity indicator.
371 */
372
373enum dmx_buffer_flags {
374 DMX_BUFFER_FLAG_HAD_CRC32_DISCARD = 1 << 0,
375 DMX_BUFFER_FLAG_TEI = 1 << 1,
376 DMX_BUFFER_PKT_COUNTER_MISMATCH = 1 << 2,
377 DMX_BUFFER_FLAG_DISCONTINUITY_DETECTED = 1 << 3,
378 DMX_BUFFER_FLAG_DISCONTINUITY_INDICATOR = 1 << 4,
379};
380
381/**
382 * struct dmx_buffer - dmx buffer info
383 *
384 * @index: id number of the buffer
385 * @bytesused: number of bytes occupied by data in the buffer (payload);
386 * @offset: for buffers with memory == DMX_MEMORY_MMAP;
387 * offset from the start of the device memory for this plane,
388 * (or a "cookie" that should be passed to mmap() as offset)
389 * @length: size in bytes of the buffer
390 * @flags: bit array of buffer flags as defined by &enum dmx_buffer_flags.
391 * Filled only at &DMX_DQBUF.
392 * @count: monotonic counter for filled buffers. Helps to identify
393 * data stream loses. Filled only at &DMX_DQBUF.
394 *
395 * Contains data exchanged by application and driver using one of the streaming
396 * I/O methods.
397 *
398 * Please notice that, for &DMX_QBUF, only @index should be filled.
399 * On &DMX_DQBUF calls, all fields will be filled by the Kernel.
400 */
401struct dmx_buffer {
402 __u32 index;
403 __u32 bytesused;
404 __u32 offset;
405 __u32 length;
406 __u32 flags;
407 __u32 count;
408};
409
410/**
411 * struct dmx_requestbuffers - request dmx buffer information
412 *
413 * @count: number of requested buffers,
414 * @size: size in bytes of the requested buffer
415 *
416 * Contains data used for requesting a dmx buffer.
417 * All reserved fields must be set to zero.
418 */
419struct dmx_requestbuffers {
420 __u32 count;
421 __u32 size;
422};
423
424/**
425 * struct dmx_exportbuffer - export of dmx buffer as DMABUF file descriptor
426 *
427 * @index: id number of the buffer
428 * @flags: flags for newly created file, currently only O_CLOEXEC is
429 * supported, refer to manual of open syscall for more details
430 * @fd: file descriptor associated with DMABUF (set by driver)
431 *
432 * Contains data used for exporting a dmx buffer as DMABUF file descriptor.
433 * The buffer is identified by a 'cookie' returned by DMX_QUERYBUF
434 * (identical to the cookie used to mmap() the buffer to userspace). All
435 * reserved fields must be set to zero. The field reserved0 is expected to
436 * become a structure 'type' allowing an alternative layout of the structure
437 * content. Therefore this field should not be used for any other extensions.
438 */
439struct dmx_exportbuffer {
440 __u32 index;
441 __u32 flags;
442 __s32 fd;
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800443};
444
445#ifdef CONFIG_AMLOGIC_DVB_COMPAT
446enum {
chuangcheng peng021cfea2023-09-12 18:37:42 +0800447 DMA_0 = 0,
448 DMA_1,
449 DMA_2,
450 DMA_3,
451 DMA_4,
452 DMA_5,
453 DMA_6,
454 DMA_7,
455 FRONTEND_TS0 = 32,
456 FRONTEND_TS1,
457 FRONTEND_TS2,
458 FRONTEND_TS3,
459 FRONTEND_TS4,
460 FRONTEND_TS5,
461 FRONTEND_TS6,
462 FRONTEND_TS7,
463 DMA_0_1 = 64,
464 DMA_1_1,
465 DMA_2_1,
466 DMA_3_1,
467 DMA_4_1,
468 DMA_5_1,
469 DMA_6_1,
470 DMA_7_1,
471 FRONTEND_TS0_1 = 96,
472 FRONTEND_TS1_1,
473 FRONTEND_TS2_1,
474 FRONTEND_TS3_1,
475 FRONTEND_TS4_1,
476 FRONTEND_TS5_1,
477 FRONTEND_TS6_1,
478 FRONTEND_TS7_1,
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800479};
Yahui Hance15e9c2020-12-08 18:08:32 +0800480
481/*define filter mem_info type*/
482enum {
chuangcheng peng021cfea2023-09-12 18:37:42 +0800483 DMX_VIDEO_TYPE = 0,
484 DMX_AUDIO_TYPE,
485 DMX_SUBTITLE_TYPE,
486 DMX_TELETEXT_TYPE,
487 DMX_SECTION_TYPE,
Yahui Hance15e9c2020-12-08 18:08:32 +0800488};
489
490struct filter_mem_info {
chuangcheng peng021cfea2023-09-12 18:37:42 +0800491 __u32 type;
492 __u32 pid;
493 struct dmx_mem_info filter_info;
Yahui Hance15e9c2020-12-08 18:08:32 +0800494};
495
496struct dmx_filter_mem_info {
chuangcheng peng021cfea2023-09-12 18:37:42 +0800497 __u32 filter_num;
498 struct filter_mem_info info[40];
Yahui Hance15e9c2020-12-08 18:08:32 +0800499};
500
501struct dvr_mem_info {
chuangcheng peng021cfea2023-09-12 18:37:42 +0800502 __u32 wp_offset;
503};
504
505struct decoder_mem_info {
506 __u32 rp_phy;
Yahui Hance15e9c2020-12-08 18:08:32 +0800507};
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800508#endif
509
510#define DMX_START _IO('o', 41)
511#define DMX_STOP _IO('o', 42)
512#define DMX_SET_FILTER _IOW('o', 43, struct dmx_sct_filter_params)
513#define DMX_SET_PES_FILTER _IOW('o', 44, struct dmx_pes_filter_params)
514#define DMX_SET_BUFFER_SIZE _IO('o', 45)
515#define DMX_GET_PES_PIDS _IOR('o', 47, __u16[5])
516#define DMX_GET_CAPS _IOR('o', 48, dmx_caps_t)
517#define DMX_SET_SOURCE _IOW('o', 49, dmx_source_t)
518#define DMX_GET_STC _IOWR('o', 50, struct dmx_stc)
519#define DMX_ADD_PID _IOW('o', 51, __u16)
520#define DMX_REMOVE_PID _IOW('o', 52, __u16)
chuangcheng peng021cfea2023-09-12 18:37:42 +0800521#if !defined(__KERNEL__)
522
523/* This is needed for legacy userspace support */
524typedef enum dmx_output dmx_output_t;
525typedef enum dmx_input dmx_input_t;
526typedef enum dmx_ts_pes dmx_pes_type_t;
527typedef struct dmx_filter dmx_filter_t;
528
529#endif
530
531#define DMX_REQBUFS _IOWR('o', 60, struct dmx_requestbuffers)
532#define DMX_QUERYBUF _IOWR('o', 61, struct dmx_buffer)
533#define DMX_EXPBUF _IOWR('o', 62, struct dmx_exportbuffer)
534#define DMX_QBUF _IOWR('o', 63, struct dmx_buffer)
535#define DMX_DQBUF _IOWR('o', 64, struct dmx_buffer)
536
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800537#ifdef CONFIG_AMLOGIC_DVB_COMPAT
538#define DMX_SET_INPUT _IO('o', 80)
539#define DMX_GET_MEM_INFO _IOR('o', 81, struct dmx_mem_info)
540#define DMX_SET_HW_SOURCE _IO('o', 82)
541#define DMX_GET_HW_SOURCE _IOR('o', 83, int)
hualing chenf9867402020-09-23 17:06:20 +0800542#define DMX_GET_FILTER_MEM_INFO _IOR('o', 84, struct dmx_filter_mem_info)
543/*just for dvr sec mem, please call before DMX_SET_PES_FILTER*/
chuangcheng peng021cfea2023-09-12 18:37:42 +0800544#define DMX_SET_SEC_MEM _IOW('o', 85, struct dmx_sec_mem)
545#define DMX_GET_DVR_MEM _IOR('o', 86, struct dvr_mem_info)
546#define DMX_REMAP_PID _IOR('o', 87, __u16[2])
547#define DMX_SET_DECODE_INFO _IOW('o', 88, struct decoder_mem_info)
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800548#endif
chuangcheng peng021cfea2023-09-12 18:37:42 +0800549#endif /* _DVBDMX_H_ */