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Chuanzhi Wang670fc042020-08-12 11:11:04 +08001/*
2 * dmx.h
3 *
4 * Copyright (C) 2000 Marcus Metzler <marcus@convergence.de>
5 * & Ralph Metzler <ralph@convergence.de>
6 * for convergence integrated media GmbH
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public License
10 * as published by the Free Software Foundation; either version 2.1
11 * of the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 *
22 */
23
24#ifndef _UAPI_DVBDMX_H_
25#define _UAPI_DVBDMX_H_
26
27#include <linux/types.h>
28#include <asm/ioctl.h>
29#ifndef __KERNEL__
30#include <time.h>
31#endif
32
33#define CONFIG_AMLOGIC_DVB_COMPAT
34#define DMX_FILTER_SIZE 16
35
36enum dmx_output
37{
hualing chen002e5b92022-02-23 17:51:21 +080038 DMX_OUT_DECODER, /* Streaming directly to decoder. */
39 DMX_OUT_TAP, /* Output going to a memory buffer */
40 /* (to be retrieved via the read command).*/
41 DMX_OUT_TS_TAP, /* Output multiplexed into a new TS */
42 /* (to be retrieved by reading from the */
43 /* logical DVR device). */
44 DMX_OUT_TSDEMUX_TAP /* Like TS_TAP but retrieved from the DMX device */
Chuanzhi Wang670fc042020-08-12 11:11:04 +080045};
46
47typedef enum dmx_output dmx_output_t;
48
49typedef enum dmx_input
50{
hualing chen002e5b92022-02-23 17:51:21 +080051 DMX_IN_FRONTEND, /* Input from a front-end device. */
52 DMX_IN_DVR /* Input from the logical DVR device. */
Chuanzhi Wang670fc042020-08-12 11:11:04 +080053} dmx_input_t;
54
55
56typedef enum dmx_ts_pes
57{
hualing chen002e5b92022-02-23 17:51:21 +080058 DMX_PES_AUDIO0,
59 DMX_PES_VIDEO0,
60 DMX_PES_TELETEXT0,
61 DMX_PES_SUBTITLE0,
62 DMX_PES_PCR0,
Chuanzhi Wang670fc042020-08-12 11:11:04 +080063
hualing chen002e5b92022-02-23 17:51:21 +080064 DMX_PES_AUDIO1,
65 DMX_PES_VIDEO1,
66 DMX_PES_TELETEXT1,
67 DMX_PES_SUBTITLE1,
68 DMX_PES_PCR1,
Chuanzhi Wang670fc042020-08-12 11:11:04 +080069
hualing chen002e5b92022-02-23 17:51:21 +080070 DMX_PES_AUDIO2,
71 DMX_PES_VIDEO2,
72 DMX_PES_TELETEXT2,
73 DMX_PES_SUBTITLE2,
74 DMX_PES_PCR2,
Chuanzhi Wang670fc042020-08-12 11:11:04 +080075
hualing chen002e5b92022-02-23 17:51:21 +080076 DMX_PES_AUDIO3,
77 DMX_PES_VIDEO3,
78 DMX_PES_TELETEXT3,
79 DMX_PES_SUBTITLE3,
80 DMX_PES_PCR3,
Chuanzhi Wang670fc042020-08-12 11:11:04 +080081
hualing chen002e5b92022-02-23 17:51:21 +080082 DMX_PES_OTHER
Chuanzhi Wang670fc042020-08-12 11:11:04 +080083} dmx_pes_type_t;
84
85#define DMX_PES_AUDIO DMX_PES_AUDIO0
86#define DMX_PES_VIDEO DMX_PES_VIDEO0
87#define DMX_PES_TELETEXT DMX_PES_TELETEXT0
88#define DMX_PES_SUBTITLE DMX_PES_SUBTITLE0
89#define DMX_PES_PCR DMX_PES_PCR0
90
91
92typedef struct dmx_filter
93{
hualing chen002e5b92022-02-23 17:51:21 +080094 __u8 filter[DMX_FILTER_SIZE];
95 __u8 mask[DMX_FILTER_SIZE];
96 __u8 mode[DMX_FILTER_SIZE];
Chuanzhi Wang670fc042020-08-12 11:11:04 +080097} dmx_filter_t;
98
99
100struct dmx_sct_filter_params
101{
hualing chen002e5b92022-02-23 17:51:21 +0800102 __u16 pid;
103 dmx_filter_t filter;
104 __u32 timeout;
105 __u32 flags;
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800106#define DMX_CHECK_CRC 1
107#define DMX_ONESHOT 2
108#define DMX_IMMEDIATE_START 4
109#define DMX_KERNEL_CLIENT 0x8000
110#ifdef CONFIG_AMLOGIC_DVB_COMPAT
111#define DMX_USE_SWFILTER 0x100
Yahui Hance15e9c2020-12-08 18:08:32 +0800112
113/*bit 8~15 for mem sec_level*/
114#define DMX_MEM_SEC_LEVEL1 (1 << 10)
Wentao MAa2889f62023-01-31 13:39:31 +0800115#define DMX_MEM_SEC_LEVEL2 (2 << 10)
116#define DMX_MEM_SEC_LEVEL3 (3 << 10)
117#define DMX_MEM_SEC_LEVEL4 (4 << 10)
118#define DMX_MEM_SEC_LEVEL5 (5 << 10)
119#define DMX_MEM_SEC_LEVEL6 (6 << 10)
120#define DMX_MEM_SEC_LEVEL7 (7 << 10)
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800121#endif
122};
123
124#ifdef CONFIG_AMLOGIC_DVB_COMPAT
125
126enum dmx_input_source {
hualing chen002e5b92022-02-23 17:51:21 +0800127 INPUT_DEMOD,
128 INPUT_LOCAL,
129 INPUT_LOCAL_SEC
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800130};
131
132/**
133 * struct dmx_non_sec_es_header - non-sec Elementary Stream (ES) Header
134 *
135 * @pts_dts_flag:[1:0], 01:pts valid, 10:dts valid
hualing chen002e5b92022-02-23 17:51:21 +0800136 * @pts: pts value
137 * @dts: dts value
138 * @len: data len
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800139 */
140struct dmx_non_sec_es_header {
hualing chen002e5b92022-02-23 17:51:21 +0800141 __u8 pts_dts_flag;
142 __u64 pts;
143 __u64 dts;
144 __u32 len;
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800145};
146
147/**
148 * struct dmx_sec_es_data - sec Elementary Stream (ES)
149 *
150 * @pts_dts_flag:[1:0], 01:pts valid, 10:dts valid
hualing chen002e5b92022-02-23 17:51:21 +0800151 * @pts: pts value
152 * @dts: dts value
153 * @buf_start: buf start addr
154 * @buf_end: buf end addr
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800155 * @data_start: data start addr
156 * @data_end: data end addr
157 */
158struct dmx_sec_es_data {
hualing chen002e5b92022-02-23 17:51:21 +0800159 __u8 pts_dts_flag;
160 __u64 pts;
161 __u64 dts;
162 __u32 buf_start;
163 __u32 buf_end;
164 __u32 data_start;
165 __u32 data_end;
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800166};
167
hualing chenf9867402020-09-23 17:06:20 +0800168struct dmx_sec_ts_data {
hualing chen002e5b92022-02-23 17:51:21 +0800169 __u32 buf_start;
170 __u32 buf_end;
171 __u32 data_start;
172 __u32 data_end;
hualing chenf9867402020-09-23 17:06:20 +0800173};
174
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800175enum dmx_audio_format {
hualing chen002e5b92022-02-23 17:51:21 +0800176 AUDIO_UNKNOWN = 0, /* unknown media */
177 AUDIO_MPX = 1, /* mpeg audio MP2/MP3 */
178 AUDIO_AC3 = 2, /* Dolby AC3/EAC3 */
179 AUDIO_AAC_ADTS = 3, /* AAC-ADTS */
180 AUDIO_AAC_LOAS = 4, /* AAC-LOAS */
181 AUDIO_DTS = 5, /* DTS */
182 AUDIO_MAX
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800183};
184
185struct dmx_mem_info {
hualing chen002e5b92022-02-23 17:51:21 +0800186 __u32 dmx_total_size;
187 __u32 dmx_buf_phy_start;
188 __u32 dmx_free_size;
189 __u32 dvb_core_total_size;
190 __u32 dvb_core_free_size;
191 __u32 wp_offset;
192 __u64 newest_pts;
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800193};
194
hualing chenf9867402020-09-23 17:06:20 +0800195struct dmx_sec_mem {
hualing chen002e5b92022-02-23 17:51:21 +0800196 __u32 buff;
197 __u32 size;
hualing chenf9867402020-09-23 17:06:20 +0800198};
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800199#endif
200
201/**
202 * struct dmx_pes_filter_params - Specifies Packetized Elementary Stream (PES)
hualing chen002e5b92022-02-23 17:51:21 +0800203 * filter parameters.
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800204 *
hualing chen002e5b92022-02-23 17:51:21 +0800205 * @pid: PID to be filtered.
206 * @input: Demux input, as specified by &enum dmx_input.
207 * @output: Demux output, as specified by &enum dmx_output.
208 * @pes_type: Type of the pes filter, as specified by &enum dmx_pes_type.
209 * @flags: Demux PES flags.
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800210 */
211struct dmx_pes_filter_params {
hualing chen002e5b92022-02-23 17:51:21 +0800212 __u16 pid;
213 dmx_input_t input;
214 dmx_output_t output;
215 dmx_pes_type_t pes_type;
216 __u32 flags;
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800217#ifdef CONFIG_AMLOGIC_DVB_COMPAT
218/*bit 8~15 for mem sec_level*/
219#define DMX_MEM_SEC_LEVEL1 (1 << 10)
Wentao MAa2889f62023-01-31 13:39:31 +0800220#define DMX_MEM_SEC_LEVEL2 (2 << 10)
221#define DMX_MEM_SEC_LEVEL3 (3 << 10)
222#define DMX_MEM_SEC_LEVEL4 (4 << 10)
223#define DMX_MEM_SEC_LEVEL5 (5 << 10)
224#define DMX_MEM_SEC_LEVEL6 (6 << 10)
225#define DMX_MEM_SEC_LEVEL7 (7 << 10)
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800226
227/*bit 16~23 for output */
228#define DMX_ES_OUTPUT (1 << 16)
229/*set raw mode, it will send the struct dmx_sec_es_data, not es data*/
hualing chen002e5b92022-02-23 17:51:21 +0800230#define DMX_OUTPUT_RAW_MODE (1 << 17)
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800231
232/*24~31 one byte for audio type, dmx_audio_format_t*/
233#define DMX_AUDIO_FORMAT_BIT 24
234
235#endif
236};
237
238typedef struct dmx_caps {
hualing chen002e5b92022-02-23 17:51:21 +0800239 __u32 caps;
240 int num_decoders;
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800241} dmx_caps_t;
242
243typedef enum dmx_source {
hualing chen002e5b92022-02-23 17:51:21 +0800244 DMX_SOURCE_FRONT0 = 0,
245 DMX_SOURCE_FRONT1,
246 DMX_SOURCE_FRONT2,
247 DMX_SOURCE_FRONT3,
248 DMX_SOURCE_DVR0 = 16,
249 DMX_SOURCE_DVR1,
250 DMX_SOURCE_DVR2,
251 DMX_SOURCE_DVR3,
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800252
253#ifdef CONFIG_AMLOGIC_DVB_COMPAT
hualing chen002e5b92022-02-23 17:51:21 +0800254 DMX_SOURCE_FRONT0_OFFSET = 100,
255 DMX_SOURCE_FRONT1_OFFSET,
256 DMX_SOURCE_FRONT2_OFFSET
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800257#endif
258} dmx_source_t;
259
260struct dmx_stc {
hualing chen002e5b92022-02-23 17:51:21 +0800261 unsigned int num; /* input : which STC? 0..N */
262 unsigned int base; /* output: divisor for stc to get 90 kHz clock */
263 __u64 stc; /* output: stc in 'base'*90 kHz units */
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800264};
265
266#ifdef CONFIG_AMLOGIC_DVB_COMPAT
267enum {
hualing chen002e5b92022-02-23 17:51:21 +0800268 DMA_0 = 0,
269 DMA_1,
270 DMA_2,
271 DMA_3,
272 DMA_4,
273 DMA_5,
274 DMA_6,
275 DMA_7,
276 FRONTEND_TS0 = 32,
277 FRONTEND_TS1,
278 FRONTEND_TS2,
279 FRONTEND_TS3,
280 FRONTEND_TS4,
281 FRONTEND_TS5,
282 FRONTEND_TS6,
283 FRONTEND_TS7,
284 DMA_0_1 = 64,
285 DMA_1_1,
286 DMA_2_1,
287 DMA_3_1,
288 DMA_4_1,
289 DMA_5_1,
290 DMA_6_1,
291 DMA_7_1,
292 FRONTEND_TS0_1 = 96,
293 FRONTEND_TS1_1,
294 FRONTEND_TS2_1,
295 FRONTEND_TS3_1,
296 FRONTEND_TS4_1,
297 FRONTEND_TS5_1,
298 FRONTEND_TS6_1,
299 FRONTEND_TS7_1,
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800300};
Yahui Hance15e9c2020-12-08 18:08:32 +0800301
302/*define filter mem_info type*/
303enum {
hualing chen002e5b92022-02-23 17:51:21 +0800304 DMX_VIDEO_TYPE = 0,
305 DMX_AUDIO_TYPE,
306 DMX_SUBTITLE_TYPE,
307 DMX_TELETEXT_TYPE,
308 DMX_SECTION_TYPE,
Yahui Hance15e9c2020-12-08 18:08:32 +0800309};
310
311struct filter_mem_info {
hualing chen002e5b92022-02-23 17:51:21 +0800312 __u32 type;
313 __u32 pid;
314 struct dmx_mem_info filter_info;
Yahui Hance15e9c2020-12-08 18:08:32 +0800315};
316
317struct dmx_filter_mem_info {
hualing chen002e5b92022-02-23 17:51:21 +0800318 __u32 filter_num;
319 struct filter_mem_info info[40];
Yahui Hance15e9c2020-12-08 18:08:32 +0800320};
321
322struct dvr_mem_info {
hualing chen002e5b92022-02-23 17:51:21 +0800323 __u32 wp_offset;
Yahui Hance15e9c2020-12-08 18:08:32 +0800324};
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800325#endif
326
327#define DMX_START _IO('o', 41)
328#define DMX_STOP _IO('o', 42)
329#define DMX_SET_FILTER _IOW('o', 43, struct dmx_sct_filter_params)
330#define DMX_SET_PES_FILTER _IOW('o', 44, struct dmx_pes_filter_params)
331#define DMX_SET_BUFFER_SIZE _IO('o', 45)
332#define DMX_GET_PES_PIDS _IOR('o', 47, __u16[5])
333#define DMX_GET_CAPS _IOR('o', 48, dmx_caps_t)
334#define DMX_SET_SOURCE _IOW('o', 49, dmx_source_t)
335#define DMX_GET_STC _IOWR('o', 50, struct dmx_stc)
336#define DMX_ADD_PID _IOW('o', 51, __u16)
337#define DMX_REMOVE_PID _IOW('o', 52, __u16)
338#ifdef CONFIG_AMLOGIC_DVB_COMPAT
339#define DMX_SET_INPUT _IO('o', 80)
340#define DMX_GET_MEM_INFO _IOR('o', 81, struct dmx_mem_info)
341#define DMX_SET_HW_SOURCE _IO('o', 82)
342#define DMX_GET_HW_SOURCE _IOR('o', 83, int)
hualing chenf9867402020-09-23 17:06:20 +0800343#define DMX_GET_FILTER_MEM_INFO _IOR('o', 84, struct dmx_filter_mem_info)
344/*just for dvr sec mem, please call before DMX_SET_PES_FILTER*/
hualing chen002e5b92022-02-23 17:51:21 +0800345#define DMX_SET_SEC_MEM _IOW('o', 85, struct dmx_sec_mem)
346#define DMX_GET_DVR_MEM _IOR('o', 86, struct dvr_mem_info)
Kihun Lee50e7d5b2021-08-05 07:59:03 +0800347#define DMX_REMAP_PID _IOR('o', 87, __u16[2])
Chuanzhi Wang670fc042020-08-12 11:11:04 +0800348#endif
349
350#endif /* _UAPI_DVBDMX_H_ */