Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | */ |
| 6 | |
| 7 | #include <stdio.h> |
| 8 | #include <stdlib.h> |
| 9 | #include <string.h> |
| 10 | #include <unistd.h> |
| 11 | |
| 12 | #include "n200_func.h" |
| 13 | #include "register.h" |
| 14 | #include "common.h" |
| 15 | #include "n200_timer.h" |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 16 | #include "gcc_compiler_attributes.h" |
Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 17 | #include "riscv_encoding.h" |
| 18 | |
| 19 | // Configure PMP to make all the address space accesable and executable |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 20 | void pmp_open_all_space(void) |
| 21 | { |
| 22 | // Config entry0 addr to all 1s to make the range cover all space |
| 23 | asm volatile("li x6, 0xffffffff" ::: "x6"); |
| 24 | asm volatile("csrw pmpaddr0, x6" :::); |
| 25 | // Config entry0 cfg to make it NAPOT address mode, and R/W/X okay |
| 26 | asm volatile("li x6, 0x7f" ::: "x6"); |
| 27 | asm volatile("csrw pmpcfg0, x6" :::); |
Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 28 | } |
| 29 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 30 | void switch_m2u_mode(void) |
| 31 | { |
| 32 | clear_csr(mstatus, MSTATUS_MPP); |
| 33 | //printf("\nIn the m2u function, the mstatus is 0x%x\n", read_csr(mstatus)); |
| 34 | //printf("\nIn the m2u function, the mepc is 0x%x\n", read_csr(mepc)); |
| 35 | asm volatile("la x6, 1f " ::: "x6"); |
| 36 | asm volatile("csrw mepc, x6" :::); |
| 37 | asm volatile("mret" :::); |
| 38 | asm volatile("1:" :::); |
Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 39 | } |
| 40 | |
| 41 | uint32_t mtime_lo(void) |
| 42 | { |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 43 | #ifdef configSOC_TIMER_AS_TICK |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 44 | return *(volatile uint32_t *)TIMERE_LOW_REG; |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 45 | #else |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 46 | return *(volatile uint32_t *)(TIMER_CTRL_ADDR + TIMER_MTIME); |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 47 | #endif |
Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 48 | } |
| 49 | |
Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 50 | uint32_t mtime_hi(void) |
| 51 | { |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 52 | #ifdef configSOC_TIMER_AS_TICK |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 53 | return *(volatile uint32_t *)TIMERE_HIG_REG; |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 54 | #else |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 55 | return *(volatile uint32_t *)(TIMER_CTRL_ADDR + TIMER_MTIME + 4); |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 56 | #endif |
Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 57 | } |
| 58 | |
| 59 | uint64_t get_timer_value(void) |
| 60 | { |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 61 | while (1) { |
| 62 | uint32_t hi = mtime_hi(); |
| 63 | uint32_t lo = mtime_lo(); |
| 64 | |
| 65 | if (hi == mtime_hi()) |
| 66 | return ((uint64_t)hi << 32) | lo; |
| 67 | } |
Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 68 | } |
| 69 | |
| 70 | uint32_t get_timer_freq(void) |
| 71 | { |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 72 | return TIMER_FREQ; |
Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 73 | } |
| 74 | |
| 75 | uint64_t get_instret_value(void) |
| 76 | { |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 77 | while (1) { |
| 78 | uint32_t hi = read_csr(minstreth); |
| 79 | uint32_t lo = read_csr(minstret); |
| 80 | |
| 81 | if (hi == read_csr(minstreth)) |
| 82 | return ((uint64_t)hi << 32) | lo; |
| 83 | } |
Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 84 | } |
| 85 | |
| 86 | uint64_t get_cycle_value(void) |
| 87 | { |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 88 | while (1) { |
| 89 | uint32_t hi = read_csr(mcycleh); |
| 90 | uint32_t lo = read_csr(mcycle); |
| 91 | |
| 92 | if (hi == read_csr(mcycleh)) |
| 93 | return ((uint64_t)hi << 32) | lo; |
| 94 | } |
Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 95 | } |
| 96 | |
| 97 | unsigned long interrupt_status_get(void) |
| 98 | { |
| 99 | return read_csr(mstatus) >> 0x3; |
| 100 | } |
| 101 | |
| 102 | void interrupt_disable(void) |
| 103 | { |
| 104 | clear_csr(mstatus, MSTATUS_MIE); |
| 105 | } |
| 106 | |
| 107 | void interrupt_enable(void) |
| 108 | { |
| 109 | set_csr(mstatus, MSTATUS_MIE); |
| 110 | } |
| 111 | |
| 112 | #ifndef CONFIG_N200_REVA |
| 113 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 114 | uint32_t __noinline measure_cpu_freq(size_t n) |
Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 115 | { |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 116 | uint32_t start_mtime, delta_mtime; |
| 117 | uint32_t mtime_freq = get_timer_freq(); |
| 118 | // Don't start measuruing until we see an mtime tick |
| 119 | uint32_t tmp = mtime_lo(); |
Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 120 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 121 | do { |
| 122 | start_mtime = mtime_lo(); |
| 123 | } while (start_mtime == tmp); |
Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 124 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 125 | uint32_t start_mcycle = read_csr(mcycle); |
Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 126 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 127 | do { |
| 128 | delta_mtime = mtime_lo() - start_mtime; |
| 129 | } while (delta_mtime < n); |
Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 130 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 131 | uint32_t delta_mcycle = read_csr(mcycle) - start_mcycle; |
Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 132 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 133 | return (delta_mcycle / delta_mtime) * mtime_freq + |
| 134 | ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime; |
Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 135 | } |
| 136 | |
| 137 | uint32_t get_cpu_freq(void) |
| 138 | { |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 139 | uint32_t cpu_freq; |
Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 140 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 141 | // warm up |
| 142 | measure_cpu_freq(1); |
| 143 | // measure for real |
| 144 | cpu_freq = measure_cpu_freq(100); |
Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 145 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame^] | 146 | return cpu_freq; |
Xiaohu.Huang | f78b48b | 2022-01-17 10:41:38 +0800 | [diff] [blame] | 147 | } |
| 148 | |
| 149 | unsigned int xPortIsIsrContext(void) |
| 150 | { |
| 151 | return (read_csr_msubmode & 0xff); |
| 152 | } |
| 153 | |
| 154 | #else |
| 155 | |
| 156 | unsigned int xPortIsIsrContext(void) |
| 157 | { |
| 158 | return read_csr_msubmode; |
| 159 | } |
| 160 | |
| 161 | #endif |