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Wenjie Qiao8a73a562023-02-23 18:37:14 +08001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
4 */
5
6#include <common.h>
7#include <command.h>
8#include <env.h>
9#include <malloc.h>
10#include <asm/byteorder.h>
11#include <amlogic/clk_measure.h>
12#include <amlogic/media/vout/hdmitx21/hdmitx.h>
Wenjie Qiao389d3ea2023-05-25 16:07:03 +080013#include <linux/delay.h>
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +080014#include <image.h>
Wenjie Qiao8a73a562023-02-23 18:37:14 +080015#include <amlogic/media/dv/dolby_vision.h>
16#include <linux/libfdt_env.h>
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +080017#include <amlogic/media/vout/dsc.h>
xiang.wu114497ab2024-02-21 14:57:05 +080018#include <amlogic/media/vout/aml_vinfo.h>
19#include <linux/arm-smccc.h>
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +080020#include <linux/compat.h>
xiang.wu1dc0df262024-07-22 19:34:22 +080021#include "../../drivers/amlogic/media/vout/hdmitx/hdmitx_common/hdmitx_check_valid.h"
xiang.wu18cf0cd12024-06-13 15:27:52 +080022#include "../../drivers/amlogic/media/vout/hdmitx/hdmitx_common/hdmitx_policy_setting.h"
Wenjie Qiao8a73a562023-02-23 18:37:14 +080023
24static unsigned char edid_raw_buf[512] = {0};
lizhi.hu506ddfa2024-07-10 21:35:41 +080025
26/*
27 * there may be outputmode/2/3 when in multi-display case,
Wenjie Qiao389d3ea2023-05-25 16:07:03 +080028 * sel_hdmimode is used to save the selected hdmi mode
29 */
xiang.wu18cf0cd12024-06-13 15:27:52 +080030static char sel_hdmimode[MESON_MODE_LEN] = {0};
Wenjie Qiao8a73a562023-02-23 18:37:14 +080031
32static void dump_full_edid(const unsigned char *buf)
33{
34 int i;
35 int blk_no;
36
37 if (!buf)
38 return;
39 blk_no = buf[126] + 1;
40 if (blk_no > 4)
41 blk_no = 4;
Wenjie Qiao389d3ea2023-05-25 16:07:03 +080042
43 if (blk_no == 2)
44 if (buf[128 + 4] == 0xe2 && buf[128 + 5] == 0x78)
45 blk_no = buf[128 + 6] + 1;
xiang.wu114497ab2024-02-21 14:57:05 +080046 if (blk_no > EDID_MAX_BLOCK)
47 blk_no = EDID_MAX_BLOCK;
Wenjie Qiao389d3ea2023-05-25 16:07:03 +080048
Wenjie Qiao8a73a562023-02-23 18:37:14 +080049 printf("dump EDID rawdata\n");
50 printf(" ");
51 for (i = 0; i < blk_no * EDID_BLK_SIZE; i++)
52 printf("%02x", buf[i]);
53 printf("\n");
54}
55
Wenjie Qiao8a73a562023-02-23 18:37:14 +080056static int do_rx_det(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
57{
58 unsigned char st = 0;
59 struct hdmitx_dev *hdev = get_hdmitx21_device();
60
61 memset(edid_raw_buf, 0, ARRAY_SIZE(edid_raw_buf));
62
lizhi.hu506ddfa2024-07-10 21:35:41 +080063 /*
64 * read edid raw data
65 * current only support read 1 byte edid data
66 */
Wenjie Qiao8a73a562023-02-23 18:37:14 +080067 st = hdev->hwop.read_edid(edid_raw_buf);
68
69 if (st) {
70 if (edid_raw_buf[250] == 0xfb && edid_raw_buf[251] == 0x0c) {
71 printf("RX is FBC\n");
72
lizhi.hu506ddfa2024-07-10 21:35:41 +080073 /* set outputmode ENV */
Wenjie Qiao8a73a562023-02-23 18:37:14 +080074 switch (edid_raw_buf[252] & 0x0f) {
75 case 0x0:
76 run_command("setenv outputmode 1080p50hz", 0);
77 break;
78 case 0x1:
79 run_command("setenv outputmode 2160p50hz420", 0);
80 break;
81 case 0x2:
82 run_command("setenv outputmode 1080p50hz44410bit", 0);
83 break;
84 case 0x3:
85 run_command("setenv outputmode 2160p50hz42010bit", 0);
86 break;
87 case 0x4:
88 run_command("setenv outputmode 2160p50hz42210bit", 0);
89 break;
90 case 0x5:
91 run_command("setenv outputmode 2160p50hz", 0);
92 break;
93 default:
94 run_command("setenv outputmode 1080p50hz", 0);
95 break;
96 }
97
lizhi.hu506ddfa2024-07-10 21:35:41 +080098 /* et RX 3D Info */
Wenjie Qiao8a73a562023-02-23 18:37:14 +080099 switch ((edid_raw_buf[252] >> 4) & 0x0f) {
100 case 0x00:
101 run_command("setenv rx_3d_info 0", 0);
102 break;
103 case 0x01:
104 run_command("setenv rx_3d_info 1", 0);
105 break;
106 case 0x02:
107 run_command("setenv rx_3d_info 2", 0);
108 break;
109 case 0x03:
110 run_command("setenv rx_3d_info 3", 0);
111 break;
112 case 0x04:
113 run_command("setenv rx_3d_info 4", 0);
114 break;
115 default:
116 break;
117 }
118
119 switch (edid_raw_buf[253]) {
120 case 0x1:
121 /*TODO*/
122 break;
123 case 0x2:
124 /*TODO*/
125 break;
126 default:
127 break;
128 }
129 }
130 } else {
131 printf("edid read failed\n");
132 }
133
134 return st;
135}
136
lizhi.hu506ddfa2024-07-10 21:35:41 +0800137int is_valid_hdmi(const char *input)
138{
139 static const char * const valid_hdmi_modes[] = {
140 "HDMI-A-A", /* venc0 */
141 "HDMI-A-B", /* venc1 */
142 "HDMI-A-C" /* venc2 */
143 };
144
145 int num_modes = ARRAY_SIZE(valid_hdmi_modes);
146 int i;
147
148 for (i = 0; i < num_modes; i++) {
149 if (strcmp(input, valid_hdmi_modes[i]) == 0)
150 return 1;
151 }
152 return 0;
153}
154
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800155static void save_default_720p(void)
156{
157 memcpy(sel_hdmimode, DEFAULT_HDMI_MODE, sizeof(DEFAULT_HDMI_MODE));
lizhi.hu506ddfa2024-07-10 21:35:41 +0800158 if (is_valid_hdmi(env_get("connector0_type"))) {
159 env_set("outputmode", DEFAULT_HDMI_MODE);
160 } else if (is_valid_hdmi(env_get("connector1_type"))) {
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800161 env_set("outputmode2", DEFAULT_HDMI_MODE);
lizhi.hu506ddfa2024-07-10 21:35:41 +0800162 } else if (is_valid_hdmi(env_get("connector2_type"))) {
163 env_set("outputmode3", DEFAULT_HDMI_MODE);
164 } else {
165 pr_info("no config connectorX_type, save default 720p outputmode\n");
166 env_set("outputmode", DEFAULT_HDMI_MODE);
167 }
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800168 env_set("colorattribute", DEFAULT_COLOR_FORMAT);
169}
170
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800171static void hdmitx_mask_rx_info(struct hdmitx_dev *hdev)
172{
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800173 if (!hdev || !hdev->para)
174 return;
175
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800176 if (env_get("colorattribute"))
177 hdmitx21_get_fmtpara(sel_hdmimode, env_get("colorattribute"));
178
lizhi.hu506ddfa2024-07-10 21:35:41 +0800179 /*
180 * when current output color depth is 8bit, mask hdr capability
181 * refer to SWPL-44445 for more detail
182 */
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800183 if (hdev->para->cd == COLORDEPTH_24B)
184 memset(&hdev->RXCap.hdr_info, 0, sizeof(struct hdr_info));
185}
186
lizhi.hu506ddfa2024-07-10 21:35:41 +0800187/*
188 * If environment qms_en is true, and RX supports QMS, and the
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800189 * output mode is BRR then enable TX QMS
190 */
191static void qms_scene_pre_process(struct hdmitx_dev *hdev)
192{
193 bool env_qms_en = 0;
194 bool rx_qms_cap = 0;
195 enum hdmi_vic qms_brr_vic = HDMI_UNKNOWN;
196 const struct hdmi_timing *t = NULL;
197 char *color = NULL;
zongdong.jiao1ac547f2024-03-06 13:43:31 +0800198 const char *i_modes[3] = {
199 "480i", "576i", "1080i",
200 };
201 char *mode;
202 int i;
203
lizhi.hu506ddfa2024-07-10 21:35:41 +0800204 /* default as 0 */
205 hdev->qms_en = 0;
zongdong.jiao1ac547f2024-03-06 13:43:31 +0800206 /* if current mode is interlaced mode, then skip QMS */
zongdong.jiao15a19b22024-05-21 15:33:05 +0800207 mode = env_get("hdmimode");
zongdong.jiao1ac547f2024-03-06 13:43:31 +0800208 if (!mode)
209 return;
210 for (i = 0; i < 3; i++) {
211 if (strstr(mode, i_modes[i]))
212 return;
213 }
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800214
215 /* check uboot environment */
216 if (env_get("qms_en") && (env_get_ulong("qms_en", 10, 0) == 1))
217 env_qms_en = 1;
218
219 rx_qms_cap = hdev->RXCap.qms;
220
221 qms_brr_vic = hdmitx_find_brr_vic(hdev->vic);
222
223 if (env_qms_en && rx_qms_cap && qms_brr_vic != HDMI_UNKNOWN)
224 hdev->qms_en = 1;
225 pr_info("QMS: env %d rx %d vic %d brr_vic %d\n", env_qms_en, rx_qms_cap,
226 hdev->vic, qms_brr_vic);
227 if (!hdev->qms_en)
228 return;
229 hdev->brr_vic = qms_brr_vic;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800230 /* reconfig the hdmi para */
231 t = hdmitx21_gettiming_from_vic(hdev->brr_vic);
232 if (!t) {
233 pr_info("not find brr_vic %d timing\n", hdev->brr_vic);
234 return;
235 }
xiang.wu168a8fa32024-05-27 17:20:43 +0800236 color = env_get("colorattribute");
zongdong.jiao15a19b22024-05-21 15:33:05 +0800237 /* save brr_vic to vic without the environment */
238 hdev->vic = hdev->brr_vic;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800239 hdev->para = hdmitx21_get_fmtpara(t->sname ? t->sname : t->name, color);
240}
241
242static void qms_scene_post_process(struct hdmitx_dev *hdev)
243{
zongdong.jiao15a19b22024-05-21 15:33:05 +0800244 const struct hdmi_timing *t = NULL;
245
lizhi.hu506ddfa2024-07-10 21:35:41 +0800246 /* Init QMS parameter */
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800247 vrr_init_qms_para(hdev);
zongdong.jiao15a19b22024-05-21 15:33:05 +0800248
249 /* set the BRR name as hdmimode and outputmode */
250 if (hdev->qms_en) {
251 t = hdmitx21_gettiming_from_vic(hdev->brr_vic);
252 if (t) {
253 env_set("hdmimode", t->sname ? t->sname : t->name);
lizhi.hu506ddfa2024-07-10 21:35:41 +0800254 /* reassing to outputmode */
255 env_set("outputmode", env_get("hdmimode"));
zongdong.jiao15a19b22024-05-21 15:33:05 +0800256 pr_info("set outputmode as %s %d\n", env_get("outputmode"), hdev->brr_vic);
257 }
258 }
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800259}
260
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800261static int do_output(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
262{
263 const struct hdmi_timing *timing = NULL;
264 struct hdmitx_dev *hdev = get_hdmitx21_device();
265
xiang.wu1a6d6f1d2023-08-04 14:13:00 +0800266#ifdef CONFIG_PXP_EMULATOR
267 hdmitx21_pxp_init(1);
268#endif
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800269 if (argc < 1)
270 return cmd_usage(cmdtp);
271
272 if (strcmp(argv[1], "list") == 0) {
273 hdev->hwop.list_support_modes();
274 } else if (strcmp(argv[1], "bist") == 0) {
275 unsigned int mode = 0;
276
277 if (strcmp(argv[2], "off") == 0)
278 mode = 0;
279 else if (strcmp(argv[2], "line") == 0)
280 mode = 2;
281 else if (strcmp(argv[2], "dot") == 0)
282 mode = 3;
283 else if (strcmp(argv[2], "x") == 0)
284 mode = 'x';
285 else if (strcmp(argv[2], "X") == 0)
286 mode = 'X';
287 else
288 mode = simple_strtoul(argv[2], NULL, 10);
289 hdev->hwop.test_bist(mode);
290 } else if (strcmp(argv[1], "prbs") == 0) {
291 hdev->para->cs = HDMI_COLORSPACE_RGB;
292 hdev->para->cd = COLORDEPTH_24B;
293 hdev->vic = HDMI_16_1920x1080p60_16x9;
294 hdmitx21_set(hdev);
295 hdev->hwop.test_prbs();
296 } else if (strncmp(argv[1], "div40", 5) == 0) {
297 bool div40 = 0;
298
299 if (argv[1][5] == '1')
300 div40 = 1;
301 hdev->hwop.set_div40(div40);
302 } else { /* "output" */
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800303 if (!hdev->pxp_mode) {
xiang.wu114497ab2024-02-21 14:57:05 +0800304 if (!hdmitx_edid_check_data_valid(0, hdev->rawedid)) {
lizhi.hu506ddfa2024-07-10 21:35:41 +0800305 /*
306 * in SWPL-34712: if EDID parsing error in kernel,
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800307 * only forcely output default mode(480p,RGB,8bit)
308 * in sysctl, not save the default mode to env.
309 * if uboot follow this rule, will cause issue OTT-19333:
310 * uboot read edid error and then output default mode,
311 * without save it mode env. if then kernel edid normal,
312 * sysctrl/kernel get mode from env, the actual output
313 * mode differs with outputmode env,it will
314 * cause display abnormal(such as stretch). so don't
315 * follow this rule in uboot, that's to say the actual
316 * output mode needs to stays with the outputmode env.
317 */
318 printf("edid parsing ng, forcely output 720p, rgb,8bit\n");
319 save_default_720p();
320 hdev->vic = HDMI_4_1280x720p60_16x9;
321 hdev->para =
322 hdmitx21_get_fmtpara("720p60hz", "rgb,8bit");
323 hdev->para->cs = HDMI_COLORSPACE_RGB;
324 hdev->para->cd = COLORDEPTH_24B;
325 hdmitx21_set(hdev);
326 return CMD_RET_SUCCESS;
327 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800328 }
329 if (!env_get("colorattribute"))
330 env_set("colorattribute", "444,8bit");
331 hdev->para = hdmitx21_get_fmtpara(argv[1], env_get("colorattribute"));
332 hdev->vic = hdev->para->timing.vic;
xiang.wu114497ab2024-02-21 14:57:05 +0800333 if (hdev->vic == HDMI_0_UNKNOWN) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800334 /* Not find VIC */
335 printf("Not find '%s' mapped VIC\n", argv[1]);
336 return CMD_RET_FAILURE;
337 }
338 if (strstr(argv[1], "hz420"))
339 hdev->para->cs = HDMI_COLORSPACE_YUV420;
340 /* S5 support over 6G, T7 not support */
341 switch (hdev->vic) {
342 case HDMI_96_3840x2160p50_16x9:
343 case HDMI_97_3840x2160p60_16x9:
344 case HDMI_101_4096x2160p50_256x135:
345 case HDMI_102_4096x2160p60_256x135:
346 case HDMI_106_3840x2160p50_64x27:
347 case HDMI_107_3840x2160p60_64x27:
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800348 if (hdev->chip_type != MESON_CPU_ID_S5) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800349 if (hdev->para->cs == HDMI_COLORSPACE_RGB ||
350 hdev->para->cs == HDMI_COLORSPACE_YUV444) {
351 if (hdev->para->cd != COLORDEPTH_24B) {
352 printf("vic %d cs %d has no cd %d\n",
353 hdev->vic,
354 hdev->para->cs,
355 hdev->para->cd);
356 hdev->para->cd = COLORDEPTH_24B;
357 printf("set cd as %d\n", COLORDEPTH_24B);
358 }
359 }
360 }
361 break;
362 default:
lizhi.hu506ddfa2024-07-10 21:35:41 +0800363 /*
364 * In Spec2.1 Table 7-34, v_active greater than or equal to 2160 and refresh
zhou.hanaccf2ad2024-06-29 11:36:03 +0800365 * rate greater than 30 will support y420
366 * Only the S5 will run this case, because 4k 50/60hz has already been
367 * filtered and only S5 support over 6G (4k 100/120hz)
368 */
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800369 timing = hdmitx21_gettiming_from_vic(hdev->vic);
370 if (!timing)
371 break;
zhou.hanaccf2ad2024-06-29 11:36:03 +0800372 if (timing->v_active >= 2160 && timing->v_freq > 30000)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800373 break;
374 if (timing->v_active >= 4320)
375 break;
376 if (hdev->para->cs == HDMI_COLORSPACE_YUV420) {
377 printf("vic %d has no cs %d\n", hdev->vic,
378 hdev->para->cs);
379 hdev->para->cs = HDMI_COLORSPACE_YUV444;
380 printf("set cs as %d\n", HDMI_COLORSPACE_YUV444);
381 }
382 break;
383 }
384 printf("set hdmitx VIC = %d CS = %d CD = %d\n",
385 hdev->vic, hdev->para->cs, hdev->para->cd);
lizhi.hu506ddfa2024-07-10 21:35:41 +0800386 /*
387 * currently, hdmi mode is always set, if
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800388 * mode set abort/exit, need to add return
389 * result of mode setting, so that vout
390 * driver will pass it to kernel, and do
391 * mode setting again when vout init in kernel
392 */
393 hdmitx21_set(hdev);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800394 qms_scene_post_process(hdev);
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800395 if (hdev->para->frl_rate && !hdev->flt_train_st) {
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800396 /* FLT training failed, need go to tmds mode */
397 printf("hdmitx frl training failed, set tmds mode\n");
xiang.wu1dba66a02024-05-28 19:53:01 +0800398 hdmitx_module_disable();
399 hdev->frl_train_fail_flag = true;
400 run_command("run init_display", 0);
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800401 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800402 }
403 return CMD_RET_SUCCESS;
404}
405
406static int do_clkmsr(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
407{
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800408 struct hdmitx_dev *hdev = get_hdmitx21_device();
409
410 if (hdev->chip_type == MESON_CPU_ID_S5) {
411 clk_msr(4);
412 clk_msr(8);
413 clk_msr(16);
414 clk_msr(27);
415 clk_msr(63);
416 clk_msr(64);
417 clk_msr(66);
418 clk_msr(68);
419 clk_msr(69);
420 clk_msr(70);
421 clk_msr(71);
422 clk_msr(72);
423 clk_msr(73);
424 clk_msr(74);
425 clk_msr(75);
426 clk_msr(76);
427 clk_msr(79);
428 clk_msr(82);
429 clk_msr(89);
430 clk_msr(90);
431 clk_msr(91);
432 clk_msr(92);
433 clk_msr(93);
434 clk_msr(94);
435 clk_msr(95);
436 return CMD_RET_SUCCESS;
437 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800438 clk_msr(51);
439 clk_msr(59);
440 clk_msr(61);
441 clk_msr(76);
442 clk_msr(77);
443 clk_msr(78);
444 clk_msr(80);
445 clk_msr(81);
446 clk_msr(82);
447 clk_msr(83);
448 clk_msr(219);
449 clk_msr(220);
450 clk_msr(221);
451 clk_msr(222);
452 return CMD_RET_SUCCESS;
453}
454
455static int do_blank(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
456{
457 struct hdmitx_dev *hdev = get_hdmitx21_device();
458
459 if (argc < 1)
460 return cmd_usage(cmdtp);
461
462 if (strcmp(argv[1], "1") == 0)
463 hdev->hwop.output_blank(1);
464 if (strcmp(argv[1], "0") == 0)
465 hdev->hwop.output_blank(0);
466
467 return CMD_RET_SUCCESS;
468}
469
470static int do_off(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
471{
472 struct hdmitx_dev *hdev = get_hdmitx21_device();
473
xiang.wu114497ab2024-02-21 14:57:05 +0800474 hdev->vic = HDMI_0_UNKNOWN;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800475 if (hdev->chip_type == MESON_CPU_ID_S5)
476 hdmitx_module_disable();
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800477 hdev->hwop.turn_off();
478 printf("turn off hdmitx\n");
479 return 1;
480}
481
482static int do_dump(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
483{
484 struct hdmitx_dev *hdev = get_hdmitx21_device();
485
486 hdev->hwop.dump_regs();
487 return 1;
488}
489
490static int do_reg(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
491{
492 unsigned long addr = 0;
493 unsigned int data = 0;
494
495 if (argc < 1)
496 return cmd_usage(cmdtp);
497
498 if (strncmp(argv[1], "rh", 2) == 0) {
499 addr = strtoul(argv[1] + 2, NULL, 16);
500 data = hdmitx21_rd_reg((unsigned int)addr);
501 printf("rd[0x%lx] 0x%x\n", addr, data);
502 }
503
504 if (strncmp(argv[1], "wh", 2) == 0) {
505 addr = strtoul(argv[1] + 2, NULL, 16);
506 data = strtoul(argv[2], NULL, 16);
507 hdmitx21_wr_reg(addr, data);
508 printf("wr[0x%lx] 0x%x\n", addr, data);
509 }
510
511 return 1;
512}
513
xiang.wu1a6d6f1d2023-08-04 14:13:00 +0800514static int do_pbist(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
515{
516 struct hdmitx_dev *hdev = get_hdmitx21_device();
517
518 if (strcmp(argv[1], "1") == 0)
519 hdmitx21_pbist_config(hdev, hdev->vic, 1);
520 if (strcmp(argv[1], "0") == 0)
521 hdmitx21_pbist_config(hdev, hdev->vic, 0);
522 return 1;
523}
524
xiang.wu1492f3642024-01-08 14:06:40 +0800525static int do_s7_clk_config(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
526{
527 struct hdmitx_dev *hdev = get_hdmitx21_device();
528
529 if (strcmp(argv[1], "1") == 0) {
530 hdev->s7_clk_config = 1;
531 pr_info("s7_clk_config = %d\n", hdev->s7_clk_config);
532 } if (strcmp(argv[1], "0") == 0) {
533 hdev->s7_clk_config = 0;
534 pr_info("s7_clk_config = %d\n", hdev->s7_clk_config);
535 }
536 return 1;
537}
538
xiang.wu114497ab2024-02-21 14:57:05 +0800539static int get_rterm(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
540{
541 struct arm_smccc_res res;
542 u8 rterm_efuse;
543
544 arm_smccc_smc(HDCPTX_IOOPR, HDMITX_GET_RTERM, 0, 0, 0, 0, 0, 0, &res);
545 rterm_efuse = (unsigned int)((res.a0) & 0xffffffff);
546 pr_info("rterm_efuse = %d\n", rterm_efuse);
547 return 1;
548}
549
xiang.wu1a6d6f1d2023-08-04 14:13:00 +0800550static int do_debug(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
551{
552 unsigned int enable_all = 0;
553 int pkt_op = 0;
554 unsigned int mov_val = 0;
555 unsigned char pb[28] = {0x46, 0xD0, 0x00, 0x00, 0x00, 0x00, 0x46, 0xD0,
556 0x00, 0x10, 0x21, 0xaa, 0x9b, 0x96, 0x19, 0xfc, 0x19, 0x75, 0xd5, 0x78,
557 0x10, 0x21, 0xaa, 0x9b, 0x96, 0x19, 0xfc, 0x19};
558 unsigned char hb[3] = {0x01, 0x02, 0x03};
559
560 if (argc < 1)
561 return cmd_usage(cmdtp);
562
563 if (strncmp(argv[1], "pkt", 3) == 0) {
564 enable_all = strtoul(argv[1] + 3, NULL, 16);
565 pkt_op = strtoul(argv[2], NULL, 16);
566 mov_val = strtoul(argv[3], NULL, 10);
567 pkt_send_position_change(enable_all, pkt_op, mov_val);
568 } else if (strncmp(argv[1], "w_dhdr", 6) == 0 ) {
569 hdmitx21_write_dhdr_sram();
570 } else if (strncmp(argv[1], "r_dhdr", 6) == 0 ) {
571 hdmitx21_read_dhdr_sram();
572 } else if (strncmp(argv[1], "t_avi", 4) == 0 ) {
573 printf("test send avi pkt\n");
574 hdmi_avi_infoframe_rawset(hb, pb);
575 } else if (strncmp(argv[1], "t_audio", 7) == 0 ) {
576 printf("test send audio pkt\n");
577 hdmi_audio_infoframe_rawset(hb, pb);
578 } else if (strncmp(argv[1], "t_sbtm", 6) == 0 ) {
579 printf("test send SBTM pkt\n");
580 hdmitx21_send_sbtm_pkt();
581 }
582
583 return 1;
584}
585
lizhi.hu506ddfa2024-07-10 21:35:41 +0800586/*
587 * step1, only select VIC which is supported in EDID
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800588 * step2, check if VIC is supported by SOC hdmitx
589 * step3, build format with basic mode/attr and check
590 * if it's supported by EDID/hdmitx_cap
591 */
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800592static void disp_cap_show(struct hdmitx_dev *hdev)
593{
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800594 if (!hdev)
595 return;
596
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800597 struct rx_cap *prxcap = &hdev->RXCap;
598 const struct hdmi_timing *timing = NULL;
599 enum hdmi_vic vic;
600 int i = 0;
601 int vic_len = prxcap->VIC_count + VESA_MAX_TIMING;
602 int *edid_vics = vmalloc(vic_len * sizeof(int));
603 enum hdmi_vic prefer_vic = HDMI_0_UNKNOWN;
604
605 memset(edid_vics, 0, vic_len * sizeof(int));
606
lizhi.hu506ddfa2024-07-10 21:35:41 +0800607 /*
608 * step1: only select VIC which is supported in EDID
609 * copy edid vic list
610 */
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800611 if (prxcap->VIC_count > 0)
612 memcpy(edid_vics, prxcap->VIC, sizeof(int) * prxcap->VIC_count);
613 for (i = 0; i < VESA_MAX_TIMING && prxcap->vesa_timing[i]; i++)
614 edid_vics[prxcap->VIC_count + i] = prxcap->vesa_timing[i];
615
616 for (i = 0; i < vic_len; i++) {
617 vic = edid_vics[i];
618 if (vic == HDMI_0_UNKNOWN)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800619 continue;
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800620
621 prefer_vic = hdmitx_get_prefer_vic(hdev, vic);
622 /* if mode_best_vic is support by RX, try 16x9 first */
zhou.hana8e91612024-04-28 14:56:45 +0000623 if (prefer_vic != vic) {
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800624 pr_info("%s: check prefer vic:%d exist, ignore [%d].\n",
625 __func__, prefer_vic, vic);
zhou.hana8e91612024-04-28 14:56:45 +0000626 continue;
627 }
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800628
629 timing = hdmitx_mode_vic_to_hdmi_timing(vic);
630 if (!timing) {
lizhi.hu506ddfa2024-07-10 21:35:41 +0800631 /* HDMITX_ERROR("%s: unsupport vic [%d]\n", __func__, vic); */
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800632 continue;
633 }
634
635 /* step2, check if VIC is supported by SOC hdmitx */
636 if (hdmitx_common_validate_vic(&hdev->tx_common, vic) != 0) {
lizhi.hu506ddfa2024-07-10 21:35:41 +0800637 /* HDMITX_ERROR("%s: vic[%d] over range.\n", __func__, vic); */
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800638 continue;
639 }
640
lizhi.hu506ddfa2024-07-10 21:35:41 +0800641 /*
642 * step3, build format with basic mode/attr and check
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800643 * if it's supported by EDID/hdmitx_cap
644 */
645 if (hdmitx_common_check_valid_para_of_vic(&hdev->tx_common, vic) != 0) {
lizhi.hu506ddfa2024-07-10 21:35:41 +0800646 /* HDMITX_ERROR("%s: vic[%d] check fmt attr failed.\n", __func__, vic); */
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800647 continue;
648 }
649
650 printf(" %s\n", timing->sname ? timing->sname : timing->name);
651
652 if (vic == prxcap->native_vic)
653 printf("*\n");
654 else
655 printf("\n");
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800656 }
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800657
xiang.wu114497ab2024-02-21 14:57:05 +0800658 printf("420_cap\n");
659 for (i = 0; i < Y420_VIC_MAX_NUM; i++) {
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800660 vic = prxcap->y420_vic[i];
xiang.wu114497ab2024-02-21 14:57:05 +0800661 printf("420vic:%d\n", vic);
662 }
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800663 vfree(edid_vics);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800664}
665
666static void vesa_cap_show(struct hdmitx_dev *hdev)
667{
668}
669
670static void dc_cap_show(struct hdmitx_dev *hdev)
671{
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800672 struct rx_cap *prxcap = &hdev->RXCap;
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800673 const struct dv_info *dv = &prxcap->dv_info;
674 const struct dv_info *dv2 = &prxcap->dv_info2;
675 int i;
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800676
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800677 /* DVI case, only rgb,8bit */
678 if (prxcap->ieeeoui != HDMI_IEEE_OUI) {
679 printf("rgb,8bit\n");
680 return;
681 }
682
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800683 if (prxcap->dc_36bit_420)
684 printf("420,12bit\n");
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800685 if (prxcap->dc_30bit_420)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800686 printf("420,10bit\n");
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800687
688 for (i = 0; i < Y420_VIC_MAX_NUM; i++) {
689 if (prxcap->y420_vic[i]) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800690 printf("420,8bit\n");
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800691 break;
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800692 }
693 }
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800694
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800695 if (prxcap->native_Mode & (1 << 5)) {
696 if (prxcap->dc_y444) {
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800697 if (prxcap->dc_36bit || dv->sup_10b_12b_444 == 0x2 ||
698 dv2->sup_10b_12b_444 == 0x2)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800699 printf("444,12bit\n");
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800700 if (prxcap->dc_30bit || dv->sup_10b_12b_444 == 0x1 ||
701 dv2->sup_10b_12b_444 == 0x1) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800702 printf("444,10bit\n");
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800703 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800704 }
705 printf("444,8bit\n");
706 }
707 /* y422, not check dc */
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800708 if (prxcap->native_Mode & (1 << 4))
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800709 printf("422,12bit\n");
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800710
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800711 if (prxcap->dc_36bit || dv->sup_10b_12b_444 == 0x2 ||
712 dv2->sup_10b_12b_444 == 0x2)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800713 printf("rgb,12bit\n");
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800714 if (prxcap->dc_30bit || dv->sup_10b_12b_444 == 0x1 ||
715 dv2->sup_10b_12b_444 == 0x1)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800716 printf("rgb,10bit\n");
717 printf("rgb,8bit\n");
718}
719
720static void aud_cap_show(struct hdmitx_dev *hdev)
721{
722}
723
724static void hdr_cap_show(struct hdmitx_dev *hdev)
725{
726 int hdr10plugsupported = 0;
727 struct hdr_info *hdr = &hdev->RXCap.hdr_info;
xiang.wu114497ab2024-02-21 14:57:05 +0800728 const struct hdr10_plus_info *hdr10p = &hdev->RXCap.hdr_info.hdr10plus_info;
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800729
730 printf("\nhdr_cap\n");
731 if (hdr10p->ieeeoui == HDR10_PLUS_IEEE_OUI &&
732 hdr10p->application_version != 0xFF)
733 hdr10plugsupported = 1;
734 printf("HDR10Plus Supported: %d\n", hdr10plugsupported);
735 printf("HDR Static Metadata:\n");
736 printf(" Supported EOTF:\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800737 printf(" Traditional SDR: %d\n", !!(hdr->hdr_support & HDR_SUP_EOTF_SDR));
738 printf(" Traditional HDR: %d\n", !!(hdr->hdr_support & HDR_SUP_EOTF_HDR));
739 printf(" SMPTE ST 2084: %d\n", !!(hdr->hdr_support & HDR_SUP_EOTF_SMPTE_ST_2084));
740 printf(" Hybrid Log-Gamma: %d\n", !!(hdr->hdr_support & HDR_SUP_EOTF_HLG));
741 printf(" Supported SMD type1: %d\n", hdr->static_metadata_type1);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800742 printf(" Luminance Data\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800743 printf(" Max: %d\n", hdr->lumi_max);
744 printf(" Avg: %d\n", hdr->lumi_avg);
745 printf(" Min: %d\n\n", hdr->lumi_min);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800746 printf("HDR Dynamic Metadata:");
747}
748
749static void _dv_cap_show(const struct dv_info *dv)
750{
751 int i;
752
753 if (dv->ieeeoui != DV_IEEE_OUI || dv->block_flag != CORRECT) {
754 printf("The Rx don't support DolbyVision\n");
755 return;
756 }
757 printf("DolbyVision RX support list:\n");
758
759 if (dv->ver == 0) {
760 printf("VSVDB Version: V%d\n", dv->ver);
761 printf("2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
762 printf("Support mode:\n");
763 printf(" DV_RGB_444_8BIT\n");
764 if (dv->sup_yuv422_12bit)
765 printf(" DV_YCbCr_422_12BIT\n");
766 }
767 if (dv->ver == 1) {
768 printf("VSVDB Version: V%d(%d-byte)\n", dv->ver, dv->length + 1);
769 if (dv->length == 0xB) {
770 printf("2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
771 printf("Support mode:\n");
772 printf(" DV_RGB_444_8BIT\n");
773 if (dv->sup_yuv422_12bit)
774 printf(" DV_YCbCr_422_12BIT\n");
775 if (dv->low_latency == 0x01)
776 printf(" LL_YCbCr_422_12BIT\n");
777 }
778
779 if (dv->length == 0xE) {
780 printf("2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
781 printf("Support mode:\n");
782 printf(" DV_RGB_444_8BIT\n");
783 if (dv->sup_yuv422_12bit)
784 printf(" DV_YCbCr_422_12BIT\n");
785 }
786 }
787 if (dv->ver == 2) {
788 printf("VSVDB Version: V%d\n", dv->ver);
789 printf("2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
790 printf("Support mode:\n");
791 if (dv->Interface != 0x00 && dv->Interface != 0x01) {
792 printf(" DV_RGB_444_8BIT\n");
793 if (dv->sup_yuv422_12bit)
794 printf(" DV_YCbCr_422_12BIT\n");
795 }
796 printf(" LL_YCbCr_422_12BIT\n");
797 if (dv->Interface == 0x01 || dv->Interface == 0x03) {
798 if (dv->sup_10b_12b_444 == 0x1)
799 printf(" LL_RGB_444_10BIT\n");
800 if (dv->sup_10b_12b_444 == 0x2)
801 printf(" LL_RGB_444_12BIT\n");
802 }
803 }
804 printf("IEEEOUI: 0x%06x\n", dv->ieeeoui);
805 printf("VSVDB: ");
806 for (i = 0; i < (dv->length + 1); i++)
807 printf("%02x", dv->rawdata[i]);
808 printf("\n");
809}
810
811static void dv_cap_show(struct hdmitx_dev *hdev)
812{
813 const struct dv_info *dv = &hdev->RXCap.dv_info;
814
815 printf("dv_cap\n");
816 if (dv->ieeeoui != DV_IEEE_OUI) {
817 printf("The Rx don't support DolbyVision\n");
818 return;
819 }
820 _dv_cap_show(dv);
821}
822
823static void edid_cap_show(struct hdmitx_dev *hdev)
824{
825 int i;
826 struct rx_cap *prxcap = &hdev->RXCap;
827
xiang.wu114497ab2024-02-21 14:57:05 +0800828 printf("Rx EDID Parse:\n");
829 printf("Rx Manufacturer Name: %s\n", prxcap->IDManufacturerName);
830 printf("Rx Product Code: %02x%02x\n",
831 prxcap->IDProductCode[0], prxcap->IDProductCode[1]);
832 printf("Rx Serial Number: %02x%02x%02x%02x\n",
833 prxcap->IDSerialNumber[0],
834 prxcap->IDSerialNumber[1],
835 prxcap->IDSerialNumber[2],
836 prxcap->IDSerialNumber[3]);
837 printf("Rx Product Name: %s\n", prxcap->ReceiverProductName);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800838
xiang.wu114497ab2024-02-21 14:57:05 +0800839 printf("Manufacture Week: %d\n", prxcap->manufacture_week);
840 printf("Manufacture Year: %d\n", prxcap->manufacture_year + 1990);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800841
xiang.wu114497ab2024-02-21 14:57:05 +0800842 printf("Physical size(mm): %d x %d\n",
843 prxcap->physical_width, prxcap->physical_height);
844
845 printf("EDID Version: %d.%d\n",
846 prxcap->edid_version, prxcap->edid_revision);
847
lizhi.hu506ddfa2024-07-10 21:35:41 +0800848/*
849 * printf(
xiang.wu114497ab2024-02-21 14:57:05 +0800850 * "EDID block number: 0x%x\n", tx_comm->EDID_buf[0x7e]);
851 *
852 *
853 * printf(
854 * "Source Physical Address[a.b.c.d]: %x.%x.%x.%x\n",
855 * hdmitx_device->hdmi_info.vsdb_phy_addr.a,
856 * hdmitx_device->hdmi_info.vsdb_phy_addr.b,
857 * hdmitx_device->hdmi_info.vsdb_phy_addr.c,
858 * hdmitx_device->hdmi_info.vsdb_phy_addr.d);
859 */
860
lizhi.hu506ddfa2024-07-10 21:35:41 +0800861 /* TODO native_vic2 */
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800862 printf("native Mode %x, VIC (native %d):\n",
xiang.wu114497ab2024-02-21 14:57:05 +0800863 prxcap->native_Mode, prxcap->native_vic);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800864
865 printf("ColorDeepSupport %x\n", prxcap->ColorDeepSupport);
866
xiang.wu114497ab2024-02-21 14:57:05 +0800867 for (i = 0; i < prxcap->VIC_count ; i++) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800868 printf("%d ", prxcap->VIC[i]);
xiang.wu114497ab2024-02-21 14:57:05 +0800869 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800870 printf("\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800871 printf("Audio {format, channel, freq, cce}\n");
872 for (i = 0; i < prxcap->AUD_count; i++) {
873 printf("{%d, %d, %x, %x}\n",
874 prxcap->RxAudioCap[i].audio_format_code,
875 prxcap->RxAudioCap[i].channel_num_max,
876 prxcap->RxAudioCap[i].freq_cc,
877 prxcap->RxAudioCap[i].cc3);
878 }
879 printf("Speaker Allocation: %x\n", prxcap->RxSpeakerAllocation);
880 printf("Vendor: 0x%x ( %s device)\n", prxcap->ieeeoui, (prxcap->ieeeoui) ? "HDMI" : "DVI");
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800881
882 printf("MaxTMDSClock1 %d MHz\n", prxcap->Max_TMDS_Clock1 * 5);
883
xiang.wu114497ab2024-02-21 14:57:05 +0800884 if (prxcap->hf_ieeeoui) {
885 printf("Vendor2: 0x%x\n",
886 prxcap->hf_ieeeoui);
887 printf("MaxTMDSClock2 %d MHz\n",
888 prxcap->Max_TMDS_Clock2 * 5);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800889 }
890
xiang.wu114497ab2024-02-21 14:57:05 +0800891 printf("MaxFRLRate: %d\n", prxcap->max_frl_rate);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800892
xiang.wu114497ab2024-02-21 14:57:05 +0800893 if (prxcap->allm)
894 printf("ALLM: %x\n", prxcap->allm);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800895
xiang.wu114497ab2024-02-21 14:57:05 +0800896 if (prxcap->cnc3)
897 printf("Game/CNC3: %x\n", prxcap->cnc3);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800898
xiang.wu114497ab2024-02-21 14:57:05 +0800899 printf("vLatency: ");
900 if (prxcap->vLatency == LATENCY_INVALID_UNKNOWN)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800901 printf(" Invalid/Unknown\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800902 else if (prxcap->vLatency == LATENCY_NOT_SUPPORT)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800903 printf(" UnSupported\n");
904 else
xiang.wu114497ab2024-02-21 14:57:05 +0800905 printf(" %d\n", prxcap->vLatency);
906
907 printf("aLatency: ");
908 if (prxcap->aLatency == LATENCY_INVALID_UNKNOWN)
909 printf(" Invalid/Unknown\n");
910 else if (prxcap->aLatency == LATENCY_NOT_SUPPORT)
911 printf(" UnSupported\n");
912 else
913 printf(" %d\n", prxcap->aLatency);
914
915 printf("i_vLatency: ");
916 if (prxcap->i_vLatency == LATENCY_INVALID_UNKNOWN)
917 printf(" Invalid/Unknown\n");
918 else if (prxcap->i_vLatency == LATENCY_NOT_SUPPORT)
919 printf(" UnSupported\n");
920 else
921 printf(" %d\n", prxcap->i_vLatency);
922
923 printf("i_aLatency: ");
924 if (prxcap->i_aLatency == LATENCY_INVALID_UNKNOWN)
925 printf(" Invalid/Unknown\n");
926 else if (prxcap->i_aLatency == LATENCY_NOT_SUPPORT)
927 printf(" UnSupported\n");
928 else
929 printf(" %d\n", prxcap->i_aLatency);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800930
931 if (prxcap->colorimetry_data)
932 printf("ColorMetry: 0x%x\n", prxcap->colorimetry_data);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800933
xiang.wu114497ab2024-02-21 14:57:05 +0800934 printf("SCDC: %x\n", prxcap->scdc_present);
935
936 printf("RR_Cap: %x\n",
937 prxcap->scdc_rr_capable);
938 printf("LTE_340M_Scramble: %x\n",
939 prxcap->lte_340mcsc_scramble);
940 /* dsc capability */
941 printf("dsc_10bpc: %d\n",
942 prxcap->dsc_10bpc);
943 printf("dsc_12bpc: %d\n",
944 prxcap->dsc_12bpc);
945 printf("dsc_16bpc: %d\n",
946 prxcap->dsc_16bpc);
947 printf("dsc_all_bpp: %d\n",
948 prxcap->dsc_all_bpp);
949 printf("dsc_native_420: %d\n",
950 prxcap->dsc_native_420);
951 printf("dsc_1p2: %d\n",
952 prxcap->dsc_1p2);
953 printf("dsc_max_slices: 0x%x(%d slices)\n",
954 prxcap->dsc_max_slices, dsc_max_slices_num[prxcap->dsc_max_slices]);
955 printf("dsc_max_frl_rate: 0x%x\n",
956 prxcap->dsc_max_frl_rate);
957 printf("dsc_total_chunk_bytes: 0x%x\n",
958 prxcap->dsc_total_chunk_bytes);
959 if (prxcap->dv_info.ieeeoui == DOVI_IEEEOUI)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800960 printf(" DolbyVision%d", prxcap->dv_info.ver);
xiang.wu114497ab2024-02-21 14:57:05 +0800961
962 if (prxcap->hdr_info2.hdr_support)
963 printf(" HDR/%d",
964 prxcap->hdr_info2.hdr_support);
965 if (prxcap->hdr_info.sbtm_info.sbtm_support)
966 printf(" SBTM");
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800967 if (prxcap->dc_y444 || prxcap->dc_30bit || prxcap->dc_30bit_420)
968 printf(" DeepColor");
969 printf("\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800970 printf("additional_vsif_num: %d\n", prxcap->additional_vsif_num);
971 printf("ifdb_present: %d\n", prxcap->ifdb_present);
lizhi.hu506ddfa2024-07-10 21:35:41 +0800972 /*
973 * for checkvalue which maybe used by application to adjust
xiang.wu114497ab2024-02-21 14:57:05 +0800974 * whether edid is changed
975 */
976 printf("checkvalue: %s\n", prxcap->hdmichecksum);
977
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800978}
979
980static int do_info(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
981{
982 struct hdmitx_dev *hdev = get_hdmitx21_device();
983 struct hdmi_format_para *para;
984
985 if (!hdev) {
986 pr_info("null hdmitx dev\n");
987 return CMD_RET_FAILURE;
988 }
989 if (!hdev->para) {
990 printf("null hdmitx para\n");
991 return CMD_RET_FAILURE;
992 }
993
994 para = hdev->para;
995 printf("current mode %s vic %d\n", para->timing.name, hdev->vic);
996 printf("cd%d cs%d cr%d\n", para->cd, para->cs, para->cr);
997 printf("enc_idx %d\n", hdev->enc_idx);
998 printf("frac_rate: %d\n", hdev->frac_rate_policy);
999 printf("Rx EDID info\n");
1000 dump_full_edid(hdev->rawedid);
1001 disp_cap_show(hdev);
1002 vesa_cap_show(hdev);
1003 aud_cap_show(hdev);
1004 hdr_cap_show(hdev);
1005 dv_cap_show(hdev);
1006 dc_cap_show(hdev);
1007 edid_cap_show(hdev);
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001008 printf("dsc policy: %d, enable: %d\n", hdev->tx_common.tx_hw->hdmi_tx_cap.dsc_policy,
1009 para->dsc_en);
1010 printf("frl_rate: %d\n", hdev->para->frl_rate);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001011 return 1;
1012}
1013
1014static int xtochar(int num, char *checksum)
1015{
1016 struct hdmitx_dev *hdev = get_hdmitx21_device();
1017
1018 if (((hdev->rawedid[num] >> 4) & 0xf) <= 9)
1019 checksum[0] = ((hdev->rawedid[num] >> 4) & 0xf) + '0';
1020 else
1021 checksum[0] = ((hdev->rawedid[num] >> 4) & 0xf) - 10 + 'a';
1022
1023 if ((hdev->rawedid[num] & 0xf) <= 9)
1024 checksum[1] = (hdev->rawedid[num] & 0xf) + '0';
1025 else
1026 checksum[1] = (hdev->rawedid[num] & 0xf) - 10 + 'a';
1027
1028 return 0;
1029}
1030
lizhi.hu506ddfa2024-07-10 21:35:41 +08001031/*
1032 * hdr_priority definition:
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001033 * strategy1: bit[3:0]
1034 * 0: original cap
1035 * 1: disable dolby vision cap
1036 * 2: disable dolby vision and hdr/hlg cap
1037 * strategy2:
1038 * bit4: 1: disable dv 0:enable dv
1039 * bit5: 1: disable hdr10/hdr10+ 0: enable hdr10/hdr10+
1040 * bit6: 1: disable hlg 0: enable hlg
1041 * bit28-bit31 choose strategy: bit[31:28]
1042 * 0: strategy1
1043 * 1: strategy2
1044 */
1045
lizhi.hu506ddfa2024-07-10 21:35:41 +08001046/*
1047 * for uboot, there is no need to dynamically change the hdr_priority as
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001048 * kernel. So below functions only implement the disable_xxx_info() function,
1049 * and leave the enable_xxx_info as blank
1050 */
1051
1052/* dv_info */
1053static void enable_dv_info(struct dv_info *des, const struct dv_info *src)
1054{
1055 if (!des || !src)
1056 return;
1057}
1058
1059static void disable_dv_info(struct dv_info *des)
1060{
1061 if (!des)
1062 return;
1063
1064 memset(des, 0, sizeof(*des));
1065}
1066
1067/* hdr10 */
1068static void enable_hdr10_info(struct hdr_info *des, const struct hdr_info *src)
1069{
1070 if (!des || !src)
1071 return;
1072}
1073
1074static void disable_hdr10_info(struct hdr_info *des)
1075{
1076 if (!des)
1077 return;
1078
xiang.wu114497ab2024-02-21 14:57:05 +08001079 des->hdr_support = des->hdr_support & 0xB;
1080 des->static_metadata_type1 = 0;
1081 des->lumi_max = 0;
1082 des->lumi_avg = 0;
1083 des->lumi_min = 0;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001084}
1085
1086/* hdr10plus */
1087static void enable_hdr10p_info(struct hdr10_plus_info *des, const struct hdr10_plus_info *src)
1088{
1089 if (!des || !src)
1090 return;
1091}
1092
1093static void disable_hdr10p_info(struct hdr10_plus_info *des)
1094{
1095 if (!des)
1096 return;
1097
1098 memset(des, 0, sizeof(*des));
1099}
1100
1101/* hlg */
1102static void enable_hlg_info(struct hdr_info *des, const struct hdr_info *src)
1103{
1104 if (!des || !src)
1105 return;
1106}
1107
1108static void disable_hlg_info(struct hdr_info *des)
1109{
1110 if (!des)
1111 return;
1112
xiang.wu114497ab2024-02-21 14:57:05 +08001113 des->hdr_support = des->hdr_support & 0x7;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001114}
1115
1116static void enable_all_hdr_info(struct rx_cap *prxcap)
1117{
1118 if (!prxcap)
1119 return;
1120}
1121
1122static void update_hdr_strategy1(struct rx_cap *prxcap, u32 strategy)
1123{
1124 if (!prxcap)
1125 return;
1126
1127 switch (strategy) {
1128 case 0:
1129 enable_all_hdr_info(prxcap);
1130 break;
1131 case 1:
1132 disable_dv_info(&prxcap->dv_info);
1133 break;
1134 case 2:
1135 disable_dv_info(&prxcap->dv_info);
1136 disable_hdr10_info(&prxcap->hdr_info);
xiang.wu114497ab2024-02-21 14:57:05 +08001137 disable_hdr10p_info(&prxcap->hdr_info.hdr10plus_info);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001138 disable_hlg_info(&prxcap->hdr_info);
1139 break;
1140 default:
1141 break;
1142 }
1143}
1144
1145static void update_hdr_strategy2(struct rx_cap *prxcap, u32 strategy)
1146{
1147 if (!prxcap)
1148 return;
1149
1150 /* bit4: 1 disable dv 0 enable dv */
1151 if (strategy & BIT(4))
1152 disable_dv_info(&prxcap->dv_info);
1153 else
1154 enable_dv_info(&prxcap->dv_info, NULL);
1155 /* bit5: 1 disable hdr10/hdr10+ 0 enable hdr10/hdr10+ */
1156 if (strategy & BIT(5)) {
1157 disable_hdr10_info(&prxcap->hdr_info);
xiang.wu114497ab2024-02-21 14:57:05 +08001158 disable_hdr10p_info(&prxcap->hdr_info.hdr10plus_info);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001159 } else {
1160 enable_hdr10_info(&prxcap->hdr_info, NULL);
xiang.wu114497ab2024-02-21 14:57:05 +08001161 enable_hdr10p_info(&prxcap->hdr_info.hdr10plus_info, NULL);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001162 }
1163 /* bit6: 1 disable hlg 0 enable hlg */
1164 if (strategy & BIT(6))
1165 disable_hlg_info(&prxcap->hdr_info);
1166 else
1167 enable_hlg_info(&prxcap->hdr_info, NULL);
1168}
1169
1170static int hdmitx_set_hdr_priority(struct rx_cap *prxcap, u32 hdr_priority)
1171{
1172 u32 choose = 0;
1173 u32 strategy = 0;
1174
1175 if (!prxcap)
1176 return -1;
1177
1178 printf("%s, set hdr_prio: %u\n", __func__, hdr_priority);
1179 /* choose strategy: bit[31:28] */
1180 choose = (hdr_priority >> 28) & 0xf;
1181 switch (choose) {
1182 case 0:
1183 strategy = hdr_priority & 0xf;
1184 update_hdr_strategy1(prxcap, strategy);
1185 break;
1186 case 1:
1187 strategy = hdr_priority & 0xf0;
1188 update_hdr_strategy2(prxcap, strategy);
1189 break;
1190 default:
1191 break;
1192 }
1193 return 0;
1194}
1195
xiang.wu100ee50f2024-05-21 19:39:45 +08001196void hdmitx_update_dv_strategy_info(struct dv_info *dv)
1197{
1198 if (dv->ver == 0) {
1199 if (dv->length == 0x19)
1200 dv->support_DV_RGB_444_8BIT = 1;
1201 }
1202
1203 if (dv->ver == 1) {
1204 if (dv->length == 0x0B) {
1205 dv->support_DV_RGB_444_8BIT = 1;
1206 if (dv->low_latency == 0x01)
1207 dv->support_LL_YCbCr_422_12BIT = 1;
1208 } else if (dv->length == 0x0E) {
1209 dv->support_DV_RGB_444_8BIT = 1;
1210 }
1211 }
1212
1213 if (dv->ver == 2) {
1214 if (dv->length >= 0x0B) {
1215 if (dv->Interface != 0x00 && dv->Interface != 0x01)
1216 dv->support_DV_RGB_444_8BIT = 1;
1217 dv->support_LL_YCbCr_422_12BIT = 1;
1218 if (dv->Interface == 0x01 || dv->Interface == 0x03) {
1219 if (dv->sup_10b_12b_444 == 0x1)
1220 dv->support_LL_RGB_444_10BIT = 1;
1221 if (dv->sup_10b_12b_444 == 0x2)
1222 dv->support_LL_RGB_444_12BIT = 1;
1223 }
1224 }
1225 }
1226}
1227
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001228static void get_parse_edid_data(struct hdmitx_dev *hdev)
1229{
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001230 hdev->hwop.read_edid(hdev->rawedid);
1231
ruofei.zhao4a2ec0c2023-10-31 19:24:41 +08001232 /* dump edid raw data */
1233 dump_full_edid(hdev->rawedid);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001234
1235 /* parse edid data */
xiang.wu114497ab2024-02-21 14:57:05 +08001236 hdmitx_edid_parse(&hdev->RXCap, hdev->rawedid);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001237
xiang.wu100ee50f2024-05-21 19:39:45 +08001238 /* Update the member variables used by the dv running strategy */
1239 hdmitx_update_dv_strategy_info(&hdev->RXCap.dv_info);
1240 hdmitx_update_dv_strategy_info(&hdev->RXCap.dv_info2);
1241
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001242 memcpy(&hdev->tx_common.rxcap, &hdev->RXCap, sizeof(hdev->tx_common.rxcap));
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001243}
1244
1245/* policy process: to find the output mode/attr/dv_type */
1246void scene_process(struct hdmitx_dev *hdev,
xiang.wu18cf0cd12024-06-13 15:27:52 +08001247 struct meson_policy_out *output)
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001248{
xiang.wu18cf0cd12024-06-13 15:27:52 +08001249 struct meson_policy_in input;
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001250
Luan Yuand9840f82024-08-14 04:20:42 -07001251 // QMS BRR selection
1252 // 120 or 60
1253 // TX cap & Rx Cap
1254 qms_scene_pre_process(hdev);
1255
xiang.wu18cf0cd12024-06-13 15:27:52 +08001256 hdmitx_set_mode_policy();
1257 memset(&input, 0, sizeof(struct meson_policy_in));
1258 get_hdmi_input(hdev, &input);
1259 hdmitx_get_policy_output(output);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001260}
1261
1262static int do_get_parse_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1263{
1264 struct hdmitx_dev *hdev = get_hdmitx21_device();
1265 unsigned char *edid = hdev->rawedid;
1266 unsigned char *store_checkvalue;
1267
xiang.wu114497ab2024-02-21 14:57:05 +08001268 memset(edid, 0, EDID_BLK_SIZE * EDID_MAX_BLOCK);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001269 unsigned int i;
1270 unsigned int checkvalue[4];
1271 unsigned int checkvalue1;
1272 unsigned int checkvalue2;
1273 char checksum[11];
1274 unsigned char def_cksum[] = {'0', 'x', '0', '0', '0', '0', '0', '0', '0', '0', '\0'};
1275 char *hdmimode;
1276 char *colorattribute;
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001277 int user_dv_mode;
1278 char *last_output_mode;
1279 char *last_colorattribute;
1280 int last_dv_status;
1281 bool over_write = false;
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001282 char dv_type[2] = {0};
xiang.wu18cf0cd12024-06-13 15:27:52 +08001283 struct meson_policy_out output;
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001284 struct hdmi_format_para *para = NULL;
1285 bool mode_support = false;
lizhi.hu506ddfa2024-07-10 21:35:41 +08001286 /*
1287 * hdmi_mode / colorattribute may be null or "none".
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001288 * if either is null or "none", it means user not
1289 * selected manually, and need to select the best
1290 * mode or colorattribute by policy
1291 */
1292 bool no_manual_output = false;
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001293
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001294 if (!hdev->hpd_state) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001295 printf("HDMI HPD low, no need parse EDID\n");
1296 return 1;
1297 }
xiang.wu18cf0cd12024-06-13 15:27:52 +08001298 memset(&output, 0, sizeof(struct meson_policy_out));
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001299
1300 get_parse_edid_data(hdev);
1301
1302 /* check if the tv has changed or anything wrong */
1303 store_checkvalue = (unsigned char *)env_get("hdmichecksum");
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001304 /* get user selected output mode/color */
1305 colorattribute = env_get("user_colorattribute");
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001306 hdmimode = env_get("hdmimode");
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001307 user_dv_mode = get_ubootenv_dv_type();
1308
1309 last_output_mode = env_get("outputmode");
1310 last_colorattribute = env_get("colorattribute");
1311 last_dv_status = get_ubootenv_dv_status();
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001312 if (!store_checkvalue)
1313 store_checkvalue = def_cksum;
1314
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001315 printf("read hdmichecksum: %s, user hdmimode: %s, colorattribute: %s, dv_type: %d\n",
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001316 store_checkvalue, hdmimode ? hdmimode : "null",
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001317 colorattribute ? colorattribute : "null", user_dv_mode);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001318
1319 for (i = 0; i < 4; i++) {
1320 if (('0' <= store_checkvalue[i * 2 + 2]) && (store_checkvalue[i * 2 + 2] <= '9'))
1321 checkvalue1 = store_checkvalue[i * 2 + 2] - '0';
1322 else
1323 checkvalue1 = store_checkvalue[i * 2 + 2] - 'W';
1324 if (('0' <= store_checkvalue[i * 2 + 3]) && (store_checkvalue[i * 2 + 3] <= '9'))
1325 checkvalue2 = store_checkvalue[i * 2 + 3] - '0';
1326 else
1327 checkvalue2 = store_checkvalue[i * 2 + 3] - 'W';
1328 checkvalue[i] = checkvalue1 * 16 + checkvalue2;
1329 }
1330
1331 if (checkvalue[0] != hdev->rawedid[0x7f] ||
1332 checkvalue[1] != hdev->rawedid[0xff] ||
1333 checkvalue[2] != hdev->rawedid[0x17f] ||
1334 checkvalue[3] != hdev->rawedid[0x1ff]) {
1335 hdev->RXCap.edid_changed = 1;
1336
1337 checksum[0] = '0';
1338 checksum[1] = 'x';
1339 for (i = 0; i < 4; i++)
1340 xtochar(0x80 * i + 0x7f, &checksum[2 * i + 2]);
1341 checksum[10] = '\0';
xiang.wu114497ab2024-02-21 14:57:05 +08001342 memcpy(hdev->RXCap.hdmichecksum, checksum, 10);
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001343 printf("TV has changed, now crc: %s\n", checksum);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001344 } else {
xiang.wu114497ab2024-02-21 14:57:05 +08001345 memcpy(hdev->RXCap.hdmichecksum, store_checkvalue, 10);
1346 printf("TV is same, checksum: %s\n", hdev->RXCap.hdmichecksum);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001347 }
1348
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001349 /* check user have selected both mode/color or not */
1350 if (!hdmimode || !strcmp(hdmimode, "none") ||
1351 !colorattribute || !strcmp(colorattribute, "none"))
1352 no_manual_output = true;
1353 else
1354 no_manual_output = false;
1355
1356 if (!no_manual_output) {
1357 /* check current user selected mode + color support or not */
1358 para = hdmitx21_get_fmtpara(hdmimode, colorattribute);
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001359 if (!hdmitx_common_validate_format_para(&hdev->tx_common, para)) {
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001360 mode_support = true;
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001361 } else {
1362 printf("saved output mode not supported!\n");
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001363 mode_support = false;
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001364 }
1365
lizhi.hu506ddfa2024-07-10 21:35:41 +08001366 /*
1367 * if user selected mode/color/dv type which saved in ubootenv of
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001368 * hdmimode/user_colorattribute/user_prefer_dv_type are different
1369 * with last actual output mode/color/dv type which saved in
1370 * ubootenv of outputmode/colorattribute/dolby_status, then it means
1371 * that the user selected format is over-writen by policy(for example:
1372 * firstly user has selected HDR priority to HDR, and select color
1373 * to rgb,12bit(now the "user_colorattribute" env will be "rgb,12bit"),
1374 * but then it selected HDR priority to DV, the actual output color
1375 * will be "444,8bit" or "422,12bit" according to dv type, and
1376 * the ubootenv "colorattribute" will be "444,8bit" or "422,12bit"),
1377 * then uboot should use the policy to select the output format,
1378 * otherwise, uboot use hdmimode/user_colorattribute/user_prefer_dv_type
1379 * env, while system use outputmode/colorattribute/dolby_status env,
1380 * there will be always a mode change during bootup
1381 */
1382 if (mode_support) {
lizhi.hu506ddfa2024-07-10 21:35:41 +08001383 /*
1384 * note that for T7 multi-display, it may store panel in
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001385 * "outputmode" env, and will always run uboot policy
1386 */
1387 if (!last_output_mode || strcmp(hdmimode, last_output_mode))
1388 over_write = true;
1389 else if (!last_colorattribute ||
1390 strcmp(colorattribute, last_colorattribute))
1391 over_write = true;
1392 else if (user_dv_mode != last_dv_status)
1393 over_write = true;
1394 else
1395 over_write = false;
1396
1397 if (over_write)
1398 printf("last output_mode:%s, colorattribute:%s, dolby_status:%d\n",
1399 last_output_mode ? last_output_mode : "null",
1400 last_colorattribute ? last_colorattribute : "null",
1401 last_dv_status);
1402 }
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001403 }
lizhi.hu506ddfa2024-07-10 21:35:41 +08001404 /*
1405 * When outputting frl mode, if frl training fails under uboot,
xiang.wu1dba66a02024-05-28 19:53:01 +08001406 * in order to ensure that it is displayed under uboot, change
1407 * to the default TMDS mode for output display. systemctrl
1408 * maintains the original 8k policy. After the subsequent systermctrl
1409 * starts running, if it is checked that the current output is not the
1410 * original frl mode, it will switch to the original frl mode.
1411 */
1412 if (hdev->frl_train_fail_flag) {
1413 save_default_720p();
1414 } else if (hdev->RXCap.edid_changed || no_manual_output || !mode_support || over_write) {
lizhi.hu506ddfa2024-07-10 21:35:41 +08001415 /*
1416 * 4 cases need to decide output by uboot mode select policy:
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001417 * 1.TV changed
1418 * 2.either hdmimode or colorattribute is NULL or "none",
1419 * which means that user have not selected mode or colorattribute,
1420 * and need to select the auto best mode or best colorattribute.
1421 * 3.user selected mode not supportted by uboot (probably
1422 * means mode select policy or edid parse between sysctrl and
1423 * uboot have some gap), then need to find proper output mode
1424 * with uboot policy.
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001425 * 4.user selected mode is over writen by system policy
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001426 */
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001427 /* find proper mode if EDID changed */
xiang.wu18cf0cd12024-06-13 15:27:52 +08001428 scene_process(hdev, &output);
xiang.wu114497ab2024-02-21 14:57:05 +08001429 env_set("hdmichecksum", hdev->RXCap.hdmichecksum);
1430 if (hdmitx_edid_check_data_valid(0, hdev->rawedid)) {
lizhi.hu506ddfa2024-07-10 21:35:41 +08001431 /*
1432 * SWPL-34712: if EDID parsing error case, not save env,
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001433 * only output default mode(480p,RGB,8bit). after
1434 * EDID read OK, systemcontrol will recover the hdmi
1435 * mode from env, to avoid keep the default hdmi output
1436 */
xiang.wu18cf0cd12024-06-13 15:27:52 +08001437 memcpy(sel_hdmimode, output.displaymode,
1438 sizeof(output.displaymode));
lizhi.hu506ddfa2024-07-10 21:35:41 +08001439 /* The outputmode must be saved based on the value of connectorX_type. */
1440 if (env_get("connector0_type") &&
1441 is_valid_hdmi(env_get("connector0_type"))) {
1442 env_set("outputmode", output.displaymode);
1443 } else if (env_get("connector1_type") &&
1444 is_valid_hdmi(env_get("connector1_type"))) {
1445 env_set("outputmode2", output.displaymode);
1446 } else if (env_get("connector2_type") &&
1447 is_valid_hdmi(env_get("connector2_type"))) {
1448 env_set("outputmode3", output.displaymode);
1449 } else {
1450 pr_info("no config connectorX_type, save default %s outputmode\n",
xiang.wu18cf0cd12024-06-13 15:27:52 +08001451 output.displaymode);
lizhi.hu506ddfa2024-07-10 21:35:41 +08001452 env_set("outputmode", output.displaymode);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001453 }
1454 env_set("colorattribute",
xiang.wu18cf0cd12024-06-13 15:27:52 +08001455 output.deepcolor);
lizhi.hu506ddfa2024-07-10 21:35:41 +08001456 /*
1457 * if change from DV TV to HDR/SDR TV, don't change
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001458 * DV status to disabled, as DV core need to be enabled.
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001459 * that's to say connect DV TV & output DV-> power down box ->
1460 * connect HDR/SDR TV -> power on box, the dolby_status
1461 * will keep the same as that when connect DV TV under follow sink.
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001462 */
xiang.wu18cf0cd12024-06-13 15:27:52 +08001463 if (output.amdv_type != get_ubootenv_dv_status() &&
1464 output.amdv_type != DOLBY_VISION_DISABLE) {
1465 sprintf(dv_type, "%d", output.amdv_type);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001466 env_set("dolby_status", dv_type);
lizhi.hu506ddfa2024-07-10 21:35:41 +08001467 /*
1468 * according to the policy of systemcontrol,
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001469 * if current DV mode is not supported by TV
1470 * EDID, DV type maybe changed to one witch
1471 * TV support, and need VPP/DV module to
1472 * update new DV output mode.
1473 */
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001474 printf("update dolby_status: %d\n",
xiang.wu18cf0cd12024-06-13 15:27:52 +08001475 output.amdv_type);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001476 }
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001477 } else {
1478 save_default_720p();
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001479 }
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001480 printf("update outputmode: %s\n", sel_hdmimode);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001481 printf("update colorattribute: %s\n", env_get("colorattribute"));
1482 printf("update hdmichecksum: %s\n", env_get("hdmichecksum"));
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001483 } else {
1484 memset(sel_hdmimode, 0, sizeof(sel_hdmimode));
1485 memcpy(sel_hdmimode, hdmimode, strlen(hdmimode));
1486 if (is_hdmi_mode(env_get("outputmode")))
1487 env_set("outputmode", hdmimode);
1488 else if (is_hdmi_mode(env_get("outputmode2")))
1489 env_set("outputmode2", hdmimode);
1490 else if (is_hdmi_mode(env_get("outputmode3")))
1491 env_set("outputmode3", hdmimode);
1492 env_set("colorattribute", colorattribute);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001493 }
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001494 env_set("save_outputmode", sel_hdmimode);
Luan Yuand9840f82024-08-14 04:20:42 -07001495 /* ubootenv dolby_status is used for is_dv_preference() decision,
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001496 * system_control save current dv output status in it.
1497 * it will be used by dv module later to decide DV output later.
1498 * if currently adaptive hdr, then we should set dolby_status to
1499 * 0, so that DV module won't enable DV.
1500 */
1501 if (get_hdr_policy() == 1)
1502 env_set("dolby_status", 0);
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001503 hdev->para = hdmitx21_get_fmtpara(sel_hdmimode, env_get("colorattribute"));
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001504 hdev->vic = hdev->para->timing.vic;
xiang.wu18cf0cd12024-06-13 15:27:52 +08001505
1506 /* update the hdr/hdr10+/dv capabilities in the end of scene_process */
1507 int hdr_priority = get_hdr_strategy_priority();
1508
1509 if (hdr_priority != -1) {
1510 hdmitx_set_hdr_priority(&hdev->RXCap, hdr_priority);
1511 memcpy(&hdev->tx_common.rxcap, &hdev->RXCap, sizeof(hdev->tx_common.rxcap));
1512 }
1513
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001514 hdmitx_mask_rx_info(hdev);
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001515 hdev->para->frl_rate = hdmitx_select_frl_rate(&hdev->para->dsc_en,
1516 hdev->tx_common.tx_hw->hdmi_tx_cap.dsc_policy,
1517 hdev->para->vic, hdev->para->cs,
1518 hdev->para->cd);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001519 return 0;
1520}
1521
1522static int do_dsc_policy(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1523{
1524 struct hdmitx_dev *hdev = get_hdmitx21_device();
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001525 struct tx_cap *txcap = &hdev->tx_common.tx_hw->hdmi_tx_cap;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001526
1527 if (argc < 1)
1528 return cmd_usage(cmdtp);
1529
1530 if (strcmp(argv[1], "0") == 0)
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001531 txcap->dsc_policy = 0;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001532 else if (strcmp(argv[1], "1") == 0)
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001533 txcap->dsc_policy = 1;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001534 else if (strcmp(argv[1], "2") == 0)
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001535 txcap->dsc_policy = 2;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001536 else if (strcmp(argv[1], "3") == 0)
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001537 txcap->dsc_policy = 3;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001538 else if (strcmp(argv[1], "4") == 0)
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001539 txcap->dsc_policy = 4;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001540 else
1541 printf("note: please set dsc policy as 0~4\n");
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001542 if (txcap->dsc_policy <= 4)
1543 printf("use dsc policy: %d\n", txcap->dsc_policy);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001544
1545 return CMD_RET_SUCCESS;
1546}
1547
1548static int do_manual_frl_rate(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1549{
1550 struct hdmitx_dev *hdev = get_hdmitx21_device();
1551 unsigned int temp = 0;
1552 char *ptr;
1553
1554 /* if rx don't support FRL, return */
1555 if (!hdev->RXCap.max_frl_rate) {
1556 printf("rx not support FRL\n");
1557 return 0;
1558 }
1559
1560 temp = strtoul(argv[1], &ptr, 16);
1561 /* forced FRL rate setting */
1562 if (temp <= 6) {
1563 hdev->manual_frl_rate = temp;
1564 pr_info("force set frl_rate as %d\n", hdev->manual_frl_rate);
1565 } else {
1566 pr_info("error: should set frl_rate in 0 ~ 6\n");
1567 }
1568 if (hdev->manual_frl_rate > hdev->RXCap.max_frl_rate)
1569 pr_info("warning: larger than rx max_frl_rate %d\n", hdev->RXCap.max_frl_rate);
1570 return 0;
1571}
1572
1573static int do_manual_dfm_type(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1574{
1575 struct hdmitx_dev *hdev = get_hdmitx21_device();
1576 unsigned int temp = 0;
1577 char *ptr;
1578
1579 temp = strtoul(argv[1], &ptr, 10);
1580 /* forced dfm_type setting */
1581 if (temp <= 2) {
1582 hdev->dfm_type = temp;
1583 pr_info("force set dfm_type as %d\n", hdev->dfm_type);
1584 } else {
1585 pr_info("error: should set frl_rate in 0 ~ 2\n");
1586 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001587 return 0;
1588}
1589
Wenjie Qiao77833902023-12-18 19:01:59 +08001590#ifdef CONFIG_EFUSE_OBJ_API
1591static int do_efuse_show(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1592{
1593 struct hdmitx_dev *hdev = get_hdmitx21_device();
1594
1595 get_hdmi_efuse(hdev);
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001596 pr_info("FEAT_DISABLE_HDMI_60HZ = %d\n", hdev->tx_common.efuse_dis_hdmi_4k60);
1597 pr_info("FEAT_DISABLE_OUTPUT_4K = %d\n", hdev->tx_common.efuse_dis_output_4k);
1598 pr_info("FEAT_DISABLE_HDCP_TX_22 = %d\n", hdev->tx_common.efuse_dis_hdcp_tx22);
1599 pr_info("FEAT_DISABLE_HDMI_TX_3D = %d\n", hdev->tx_common.efuse_dis_hdmi_tx3d);
1600 pr_info("FEAT_DISABLE_HDMI = %d\n", hdev->tx_common.efuse_dis_hdcp_tx14);
Wenjie Qiao77833902023-12-18 19:01:59 +08001601
1602 return 0;
1603}
1604#endif
1605
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001606static cmd_tbl_t cmd_hdmi_sub[] = {
1607 U_BOOT_CMD_MKENT(hpd, 1, 1, do_hpd_detect, "", ""),
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001608 U_BOOT_CMD_MKENT(rx_det, 1, 1, do_rx_det, "", ""),
1609 U_BOOT_CMD_MKENT(output, 3, 1, do_output, "", ""),
1610 U_BOOT_CMD_MKENT(clkmsr, 3, 1, do_clkmsr, "", ""),
1611 U_BOOT_CMD_MKENT(blank, 3, 1, do_blank, "", ""),
1612 U_BOOT_CMD_MKENT(off, 1, 1, do_off, "", ""),
1613 U_BOOT_CMD_MKENT(dump, 1, 1, do_dump, "", ""),
1614 U_BOOT_CMD_MKENT(info, 1, 1, do_info, "", ""),
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001615 U_BOOT_CMD_MKENT(reg, 3, 1, do_reg, "", ""),
1616 U_BOOT_CMD_MKENT(get_parse_edid, 1, 1, do_get_parse_edid, "", ""),
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001617 U_BOOT_CMD_MKENT(dsc_policy, 1, 1, do_dsc_policy, "", ""),
1618 U_BOOT_CMD_MKENT(frl_rate, 1, 1, do_manual_frl_rate, "", ""),
1619 U_BOOT_CMD_MKENT(dfm_type, 1, 1, do_manual_dfm_type, "", ""),
Wenjie Qiao77833902023-12-18 19:01:59 +08001620#ifdef CONFIG_EFUSE_OBJ_API
1621 U_BOOT_CMD_MKENT(efuse, 1, 1, do_efuse_show, "", ""),
1622#endif
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001623 U_BOOT_CMD_MKENT(pbist, 3, 1, do_pbist, "", ""),
1624 U_BOOT_CMD_MKENT(debug, 3, 1, do_debug, "", ""),
xiang.wu1492f3642024-01-08 14:06:40 +08001625 U_BOOT_CMD_MKENT(s7_clk_config, 3, 1, do_s7_clk_config, "", ""),
xiang.wu114497ab2024-02-21 14:57:05 +08001626 U_BOOT_CMD_MKENT(get_rterm, 3, 1, get_rterm, "", ""),
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001627};
1628
1629static int do_hdmitx(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1630{
1631 cmd_tbl_t *c;
1632
1633 if (argc < 2)
1634 return cmd_usage(cmdtp);
1635
1636 argc--;
1637 argv++;
1638
1639 c = find_cmd_tbl(argv[0], &cmd_hdmi_sub[0], ARRAY_SIZE(cmd_hdmi_sub));
1640
1641 if (c)
1642 return c->cmd(cmdtp, flag, argc, argv);
1643 else
1644 return cmd_usage(cmdtp);
1645}
1646
1647U_BOOT_CMD(hdmitx, CONFIG_SYS_MAXARGS, 0, do_hdmitx,
1648 "HDMITX sub-system",
1649 "hdmitx version:20200618\n"
1650 "hdmitx hpd\n"
1651 " Detect hdmi rx plug-in\n"
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001652 "hdmitx output [list | FORMAT | bist PATTERN]\n"
1653 " list: list support formats\n"
1654 " FORMAT can be 720p60/50hz, 1080i60/50hz, 1080p60hz, etc\n"
1655 " extend with 8bits/10bits, y444/y422/y420/rgb\n"
1656 " such as 2160p60hz,10bits,y420\n"
1657 " PATTERN: can be as: line, dot, off, or 1920(width)\n"
1658 "hdmitx blank [0|1]\n"
1659 " 1: output blank 0: output normal\n"
1660 "hdmitx clkmsr\n"
1661 " show hdmitx clocks\n"
1662 "hdmitx off\n"
1663 " Turn off hdmitx output\n"
1664 "hdmitx info\n"
1665 " current mode info\n"
1666 "hdmitx rx_det\n"
1667 " Auto detect if RX is FBC and set outputmode\n"
1668);
1669
1670struct hdr_info *hdmitx_get_rx_hdr_info(void)
1671{
1672 struct hdmitx_dev *hdev = get_hdmitx21_device();
1673
1674 return &hdev->RXCap.hdr_info;
1675}
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001676
1677static int do_list_dsc_mode(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1678{
1679#ifdef CONFIG_AML_DSC_ENC
1680 dsc_enc_cap_show();
1681#endif
1682 return 0;
1683}
1684
1685static int do_dsc_debug(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1686{
1687#ifdef CONFIG_AML_DSC_ENC
1688 dsc_debug(argc - 1, argv + 1);
1689#endif
1690 return 0;
1691}
1692
1693static cmd_tbl_t cmd_dsc_sub[] = {
1694 U_BOOT_CMD_MKENT(list_mode, 1, 1, do_list_dsc_mode, "", ""),
1695 U_BOOT_CMD_MKENT(dbg, 20, 1, do_dsc_debug, "", ""),
1696};
1697
1698static int do_dsc_enc(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1699{
1700 cmd_tbl_t *c;
1701
1702 if (argc < 2)
1703 return cmd_usage(cmdtp);
1704
1705 argc--;
1706 argv++;
1707
1708 c = find_cmd_tbl(argv[0], &cmd_dsc_sub[0], ARRAY_SIZE(cmd_dsc_sub));
1709
1710 if (c)
1711 return c->cmd(cmdtp, flag, argc, argv);
1712 else
1713 return cmd_usage(cmdtp);
1714}
1715
1716U_BOOT_CMD(dsc, CONFIG_SYS_MAXARGS, 0, do_dsc_enc,
1717 "dsc cmd",
1718 "dsc help function\n"
1719 "dsc dbg state\n"
1720 " dump dsc status\n"
1721 "dsc dbg dump_reg\n"
1722 " dump dsc registers and venc registers\n"
1723 "dsc dbg read addr\n"
1724 " read dsc asic register\n"
1725 "dsc dbg write addr value\n"
1726 " write dsc asic register\n"
1727 "dsc dbg rst_dsc\n"
1728 " reset dsc enc\n"
1729 "dsc list_mode\n"
1730 " show supported dsc encode mode list\n"
1731);
1732