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Wenjie Qiao8a73a562023-02-23 18:37:14 +08001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
4 */
5
6#include <common.h>
7#include <command.h>
8#include <env.h>
9#include <malloc.h>
10#include <asm/byteorder.h>
11#include <amlogic/clk_measure.h>
12#include <amlogic/media/vout/hdmitx21/hdmitx.h>
Wenjie Qiao389d3ea2023-05-25 16:07:03 +080013#include <linux/delay.h>
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +080014#include <image.h>
Wenjie Qiao8a73a562023-02-23 18:37:14 +080015#include <amlogic/media/dv/dolby_vision.h>
16#include <linux/libfdt_env.h>
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +080017#include <amlogic/media/vout/dsc.h>
xiang.wu114497ab2024-02-21 14:57:05 +080018#include <amlogic/media/vout/aml_vinfo.h>
19#include <linux/arm-smccc.h>
Wenjie Qiao8a73a562023-02-23 18:37:14 +080020
21static unsigned char edid_raw_buf[512] = {0};
Wenjie Qiao389d3ea2023-05-25 16:07:03 +080022/* there may be outputmode/2/3 when in multi-display case,
23 * sel_hdmimode is used to save the selected hdmi mode
24 */
25static char sel_hdmimode[MODE_LEN] = {0};
Wenjie Qiao8a73a562023-02-23 18:37:14 +080026
27static void dump_full_edid(const unsigned char *buf)
28{
29 int i;
30 int blk_no;
31
32 if (!buf)
33 return;
34 blk_no = buf[126] + 1;
35 if (blk_no > 4)
36 blk_no = 4;
Wenjie Qiao389d3ea2023-05-25 16:07:03 +080037
38 if (blk_no == 2)
39 if (buf[128 + 4] == 0xe2 && buf[128 + 5] == 0x78)
40 blk_no = buf[128 + 6] + 1;
xiang.wu114497ab2024-02-21 14:57:05 +080041 if (blk_no > EDID_MAX_BLOCK)
42 blk_no = EDID_MAX_BLOCK;
Wenjie Qiao389d3ea2023-05-25 16:07:03 +080043
Wenjie Qiao8a73a562023-02-23 18:37:14 +080044 printf("dump EDID rawdata\n");
45 printf(" ");
46 for (i = 0; i < blk_no * EDID_BLK_SIZE; i++)
47 printf("%02x", buf[i]);
48 printf("\n");
49}
50
51static int do_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
52{
53 unsigned char st = 0;
54 struct hdmitx_dev *hdev = get_hdmitx21_device();
55
56 memset(edid_raw_buf, 0, ARRAY_SIZE(edid_raw_buf));
57
58 st = hdev->hwop.read_edid(edid_raw_buf);
59
60 if (!st)
61 printf("edid read failed\n");
62
63 return st;
64}
65
66static int do_rx_det(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
67{
68 unsigned char st = 0;
69 struct hdmitx_dev *hdev = get_hdmitx21_device();
70
71 memset(edid_raw_buf, 0, ARRAY_SIZE(edid_raw_buf));
72
73 // read edid raw data
74 // current only support read 1 byte edid data
75 st = hdev->hwop.read_edid(edid_raw_buf);
76
77 if (st) {
78 if (edid_raw_buf[250] == 0xfb && edid_raw_buf[251] == 0x0c) {
79 printf("RX is FBC\n");
80
81 // set outputmode ENV
82 switch (edid_raw_buf[252] & 0x0f) {
83 case 0x0:
84 run_command("setenv outputmode 1080p50hz", 0);
85 break;
86 case 0x1:
87 run_command("setenv outputmode 2160p50hz420", 0);
88 break;
89 case 0x2:
90 run_command("setenv outputmode 1080p50hz44410bit", 0);
91 break;
92 case 0x3:
93 run_command("setenv outputmode 2160p50hz42010bit", 0);
94 break;
95 case 0x4:
96 run_command("setenv outputmode 2160p50hz42210bit", 0);
97 break;
98 case 0x5:
99 run_command("setenv outputmode 2160p50hz", 0);
100 break;
101 default:
102 run_command("setenv outputmode 1080p50hz", 0);
103 break;
104 }
105
106 /*et RX 3D Info*/
107 switch ((edid_raw_buf[252] >> 4) & 0x0f) {
108 case 0x00:
109 run_command("setenv rx_3d_info 0", 0);
110 break;
111 case 0x01:
112 run_command("setenv rx_3d_info 1", 0);
113 break;
114 case 0x02:
115 run_command("setenv rx_3d_info 2", 0);
116 break;
117 case 0x03:
118 run_command("setenv rx_3d_info 3", 0);
119 break;
120 case 0x04:
121 run_command("setenv rx_3d_info 4", 0);
122 break;
123 default:
124 break;
125 }
126
127 switch (edid_raw_buf[253]) {
128 case 0x1:
129 /*TODO*/
130 break;
131 case 0x2:
132 /*TODO*/
133 break;
134 default:
135 break;
136 }
137 }
138 } else {
139 printf("edid read failed\n");
140 }
141
142 return st;
143}
144
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800145static void save_default_720p(void)
146{
147 memcpy(sel_hdmimode, DEFAULT_HDMI_MODE, sizeof(DEFAULT_HDMI_MODE));
148 if (is_hdmi_mode(env_get("outputmode")))
149 env_set("outputmode", DEFAULT_HDMI_MODE);
150 else if (is_hdmi_mode(env_get("outputmode2")))
151 env_set("outputmode2", DEFAULT_HDMI_MODE);
152 else if (is_hdmi_mode(env_get("outputmode3")))
153 env_set("outputmode3", DEFAULT_HDMI_MODE);
154 env_set("colorattribute", DEFAULT_COLOR_FORMAT);
155}
156
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800157static void hdmitx_mask_rx_info(struct hdmitx_dev *hdev)
158{
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800159 if (!hdev || !hdev->para)
160 return;
161
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800162 if (env_get("colorattribute"))
163 hdmitx21_get_fmtpara(sel_hdmimode, env_get("colorattribute"));
164
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800165 /* when current output color depth is 8bit, mask hdr capability */
166 /* refer to SWPL-44445 for more detail */
167 if (hdev->para->cd == COLORDEPTH_24B)
168 memset(&hdev->RXCap.hdr_info, 0, sizeof(struct hdr_info));
169}
170
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800171/* If environment qms_en is true, and RX supports QMS, and the
172 * output mode is BRR then enable TX QMS
173 */
174static void qms_scene_pre_process(struct hdmitx_dev *hdev)
175{
176 bool env_qms_en = 0;
177 bool rx_qms_cap = 0;
178 enum hdmi_vic qms_brr_vic = HDMI_UNKNOWN;
179 const struct hdmi_timing *t = NULL;
180 char *color = NULL;
zongdong.jiao1ac547f2024-03-06 13:43:31 +0800181 const char *i_modes[3] = {
182 "480i", "576i", "1080i",
183 };
184 char *mode;
185 int i;
186
zongdong.jiao15a19b22024-05-21 15:33:05 +0800187 hdev->qms_en = 0; /* default as 0 */
zongdong.jiao1ac547f2024-03-06 13:43:31 +0800188 /* if current mode is interlaced mode, then skip QMS */
zongdong.jiao15a19b22024-05-21 15:33:05 +0800189 mode = env_get("hdmimode");
zongdong.jiao1ac547f2024-03-06 13:43:31 +0800190 if (!mode)
191 return;
192 for (i = 0; i < 3; i++) {
193 if (strstr(mode, i_modes[i]))
194 return;
195 }
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800196
197 /* check uboot environment */
198 if (env_get("qms_en") && (env_get_ulong("qms_en", 10, 0) == 1))
199 env_qms_en = 1;
200
201 rx_qms_cap = hdev->RXCap.qms;
202
203 qms_brr_vic = hdmitx_find_brr_vic(hdev->vic);
204
205 if (env_qms_en && rx_qms_cap && qms_brr_vic != HDMI_UNKNOWN)
206 hdev->qms_en = 1;
207 pr_info("QMS: env %d rx %d vic %d brr_vic %d\n", env_qms_en, rx_qms_cap,
208 hdev->vic, qms_brr_vic);
209 if (!hdev->qms_en)
210 return;
211 hdev->brr_vic = qms_brr_vic;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800212 /* reconfig the hdmi para */
213 t = hdmitx21_gettiming_from_vic(hdev->brr_vic);
214 if (!t) {
215 pr_info("not find brr_vic %d timing\n", hdev->brr_vic);
216 return;
217 }
xiang.wu168a8fa32024-05-27 17:20:43 +0800218 color = env_get("colorattribute");
zongdong.jiao15a19b22024-05-21 15:33:05 +0800219 /* save brr_vic to vic without the environment */
220 hdev->vic = hdev->brr_vic;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800221 hdev->para = hdmitx21_get_fmtpara(t->sname ? t->sname : t->name, color);
222}
223
224static void qms_scene_post_process(struct hdmitx_dev *hdev)
225{
zongdong.jiao15a19b22024-05-21 15:33:05 +0800226 const struct hdmi_timing *t = NULL;
227
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800228 // Init QMS parameter
229 vrr_init_qms_para(hdev);
zongdong.jiao15a19b22024-05-21 15:33:05 +0800230
231 /* set the BRR name as hdmimode and outputmode */
232 if (hdev->qms_en) {
233 t = hdmitx21_gettiming_from_vic(hdev->brr_vic);
234 if (t) {
235 env_set("hdmimode", t->sname ? t->sname : t->name);
236 env_set("outputmode", env_get("hdmimode")); /* reassing to outputmode */
237 pr_info("set outputmode as %s %d\n", env_get("outputmode"), hdev->brr_vic);
238 }
239 }
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800240}
241
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800242static int do_output(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
243{
244 const struct hdmi_timing *timing = NULL;
245 struct hdmitx_dev *hdev = get_hdmitx21_device();
246
xiang.wu1a6d6f1d2023-08-04 14:13:00 +0800247#ifdef CONFIG_PXP_EMULATOR
248 hdmitx21_pxp_init(1);
249#endif
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800250 if (argc < 1)
251 return cmd_usage(cmdtp);
252
253 if (strcmp(argv[1], "list") == 0) {
254 hdev->hwop.list_support_modes();
255 } else if (strcmp(argv[1], "bist") == 0) {
256 unsigned int mode = 0;
257
258 if (strcmp(argv[2], "off") == 0)
259 mode = 0;
260 else if (strcmp(argv[2], "line") == 0)
261 mode = 2;
262 else if (strcmp(argv[2], "dot") == 0)
263 mode = 3;
264 else if (strcmp(argv[2], "x") == 0)
265 mode = 'x';
266 else if (strcmp(argv[2], "X") == 0)
267 mode = 'X';
268 else
269 mode = simple_strtoul(argv[2], NULL, 10);
270 hdev->hwop.test_bist(mode);
271 } else if (strcmp(argv[1], "prbs") == 0) {
272 hdev->para->cs = HDMI_COLORSPACE_RGB;
273 hdev->para->cd = COLORDEPTH_24B;
274 hdev->vic = HDMI_16_1920x1080p60_16x9;
275 hdmitx21_set(hdev);
276 hdev->hwop.test_prbs();
277 } else if (strncmp(argv[1], "div40", 5) == 0) {
278 bool div40 = 0;
279
280 if (argv[1][5] == '1')
281 div40 = 1;
282 hdev->hwop.set_div40(div40);
283 } else { /* "output" */
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800284 if (!hdev->pxp_mode) {
xiang.wu114497ab2024-02-21 14:57:05 +0800285 if (!hdmitx_edid_check_data_valid(0, hdev->rawedid)) {
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800286 /* in SWPL-34712: if EDID parsing error in kernel,
287 * only forcely output default mode(480p,RGB,8bit)
288 * in sysctl, not save the default mode to env.
289 * if uboot follow this rule, will cause issue OTT-19333:
290 * uboot read edid error and then output default mode,
291 * without save it mode env. if then kernel edid normal,
292 * sysctrl/kernel get mode from env, the actual output
293 * mode differs with outputmode env,it will
294 * cause display abnormal(such as stretch). so don't
295 * follow this rule in uboot, that's to say the actual
296 * output mode needs to stays with the outputmode env.
297 */
298 printf("edid parsing ng, forcely output 720p, rgb,8bit\n");
299 save_default_720p();
300 hdev->vic = HDMI_4_1280x720p60_16x9;
301 hdev->para =
302 hdmitx21_get_fmtpara("720p60hz", "rgb,8bit");
303 hdev->para->cs = HDMI_COLORSPACE_RGB;
304 hdev->para->cd = COLORDEPTH_24B;
305 hdmitx21_set(hdev);
306 return CMD_RET_SUCCESS;
307 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800308 }
309 if (!env_get("colorattribute"))
310 env_set("colorattribute", "444,8bit");
311 hdev->para = hdmitx21_get_fmtpara(argv[1], env_get("colorattribute"));
312 hdev->vic = hdev->para->timing.vic;
xiang.wu114497ab2024-02-21 14:57:05 +0800313 if (hdev->vic == HDMI_0_UNKNOWN) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800314 /* Not find VIC */
315 printf("Not find '%s' mapped VIC\n", argv[1]);
316 return CMD_RET_FAILURE;
317 }
318 if (strstr(argv[1], "hz420"))
319 hdev->para->cs = HDMI_COLORSPACE_YUV420;
320 /* S5 support over 6G, T7 not support */
321 switch (hdev->vic) {
322 case HDMI_96_3840x2160p50_16x9:
323 case HDMI_97_3840x2160p60_16x9:
324 case HDMI_101_4096x2160p50_256x135:
325 case HDMI_102_4096x2160p60_256x135:
326 case HDMI_106_3840x2160p50_64x27:
327 case HDMI_107_3840x2160p60_64x27:
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800328 if (hdev->chip_type != MESON_CPU_ID_S5) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800329 if (hdev->para->cs == HDMI_COLORSPACE_RGB ||
330 hdev->para->cs == HDMI_COLORSPACE_YUV444) {
331 if (hdev->para->cd != COLORDEPTH_24B) {
332 printf("vic %d cs %d has no cd %d\n",
333 hdev->vic,
334 hdev->para->cs,
335 hdev->para->cd);
336 hdev->para->cd = COLORDEPTH_24B;
337 printf("set cd as %d\n", COLORDEPTH_24B);
338 }
339 }
340 }
341 break;
342 default:
343 /* In Spec2.1 Table 7-34, greater than 2160p30hz will support y420 */
344 timing = hdmitx21_gettiming_from_vic(hdev->vic);
345 if (!timing)
346 break;
347 if (timing->v_active > 2160 && timing->v_freq > 30000)
348 break;
349 if (timing->v_active >= 4320)
350 break;
351 if (hdev->para->cs == HDMI_COLORSPACE_YUV420) {
352 printf("vic %d has no cs %d\n", hdev->vic,
353 hdev->para->cs);
354 hdev->para->cs = HDMI_COLORSPACE_YUV444;
355 printf("set cs as %d\n", HDMI_COLORSPACE_YUV444);
356 }
357 break;
358 }
359 printf("set hdmitx VIC = %d CS = %d CD = %d\n",
360 hdev->vic, hdev->para->cs, hdev->para->cd);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800361 qms_scene_pre_process(hdev);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800362 /* currently, hdmi mode is always set, if
363 * mode set abort/exit, need to add return
364 * result of mode setting, so that vout
365 * driver will pass it to kernel, and do
366 * mode setting again when vout init in kernel
367 */
368 hdmitx21_set(hdev);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800369 qms_scene_post_process(hdev);
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800370 if (hdev->frl_rate && !hdev->flt_train_st) {
371 /* FLT training failed, need go to tmds mode */
372 printf("hdmitx frl training failed, set tmds mode\n");
xiang.wu1dba66a02024-05-28 19:53:01 +0800373 hdmitx_module_disable();
374 hdev->frl_train_fail_flag = true;
375 run_command("run init_display", 0);
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800376 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800377 }
378 return CMD_RET_SUCCESS;
379}
380
381static int do_clkmsr(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
382{
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800383 struct hdmitx_dev *hdev = get_hdmitx21_device();
384
385 if (hdev->chip_type == MESON_CPU_ID_S5) {
386 clk_msr(4);
387 clk_msr(8);
388 clk_msr(16);
389 clk_msr(27);
390 clk_msr(63);
391 clk_msr(64);
392 clk_msr(66);
393 clk_msr(68);
394 clk_msr(69);
395 clk_msr(70);
396 clk_msr(71);
397 clk_msr(72);
398 clk_msr(73);
399 clk_msr(74);
400 clk_msr(75);
401 clk_msr(76);
402 clk_msr(79);
403 clk_msr(82);
404 clk_msr(89);
405 clk_msr(90);
406 clk_msr(91);
407 clk_msr(92);
408 clk_msr(93);
409 clk_msr(94);
410 clk_msr(95);
411 return CMD_RET_SUCCESS;
412 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800413 clk_msr(51);
414 clk_msr(59);
415 clk_msr(61);
416 clk_msr(76);
417 clk_msr(77);
418 clk_msr(78);
419 clk_msr(80);
420 clk_msr(81);
421 clk_msr(82);
422 clk_msr(83);
423 clk_msr(219);
424 clk_msr(220);
425 clk_msr(221);
426 clk_msr(222);
427 return CMD_RET_SUCCESS;
428}
429
430static int do_blank(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
431{
432 struct hdmitx_dev *hdev = get_hdmitx21_device();
433
434 if (argc < 1)
435 return cmd_usage(cmdtp);
436
437 if (strcmp(argv[1], "1") == 0)
438 hdev->hwop.output_blank(1);
439 if (strcmp(argv[1], "0") == 0)
440 hdev->hwop.output_blank(0);
441
442 return CMD_RET_SUCCESS;
443}
444
445static int do_off(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
446{
447 struct hdmitx_dev *hdev = get_hdmitx21_device();
448
xiang.wu114497ab2024-02-21 14:57:05 +0800449 hdev->vic = HDMI_0_UNKNOWN;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800450 if (hdev->chip_type == MESON_CPU_ID_S5)
451 hdmitx_module_disable();
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800452 hdev->hwop.turn_off();
453 printf("turn off hdmitx\n");
454 return 1;
455}
456
457static int do_dump(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
458{
459 struct hdmitx_dev *hdev = get_hdmitx21_device();
460
461 hdev->hwop.dump_regs();
462 return 1;
463}
464
465static int do_reg(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
466{
467 unsigned long addr = 0;
468 unsigned int data = 0;
469
470 if (argc < 1)
471 return cmd_usage(cmdtp);
472
473 if (strncmp(argv[1], "rh", 2) == 0) {
474 addr = strtoul(argv[1] + 2, NULL, 16);
475 data = hdmitx21_rd_reg((unsigned int)addr);
476 printf("rd[0x%lx] 0x%x\n", addr, data);
477 }
478
479 if (strncmp(argv[1], "wh", 2) == 0) {
480 addr = strtoul(argv[1] + 2, NULL, 16);
481 data = strtoul(argv[2], NULL, 16);
482 hdmitx21_wr_reg(addr, data);
483 printf("wr[0x%lx] 0x%x\n", addr, data);
484 }
485
486 return 1;
487}
488
xiang.wu1a6d6f1d2023-08-04 14:13:00 +0800489static int do_pbist(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
490{
491 struct hdmitx_dev *hdev = get_hdmitx21_device();
492
493 if (strcmp(argv[1], "1") == 0)
494 hdmitx21_pbist_config(hdev, hdev->vic, 1);
495 if (strcmp(argv[1], "0") == 0)
496 hdmitx21_pbist_config(hdev, hdev->vic, 0);
497 return 1;
498}
499
xiang.wu1492f3642024-01-08 14:06:40 +0800500static int do_s7_clk_config(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
501{
502 struct hdmitx_dev *hdev = get_hdmitx21_device();
503
504 if (strcmp(argv[1], "1") == 0) {
505 hdev->s7_clk_config = 1;
506 pr_info("s7_clk_config = %d\n", hdev->s7_clk_config);
507 } if (strcmp(argv[1], "0") == 0) {
508 hdev->s7_clk_config = 0;
509 pr_info("s7_clk_config = %d\n", hdev->s7_clk_config);
510 }
511 return 1;
512}
513
xiang.wu114497ab2024-02-21 14:57:05 +0800514static int get_rterm(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
515{
516 struct arm_smccc_res res;
517 u8 rterm_efuse;
518
519 arm_smccc_smc(HDCPTX_IOOPR, HDMITX_GET_RTERM, 0, 0, 0, 0, 0, 0, &res);
520 rterm_efuse = (unsigned int)((res.a0) & 0xffffffff);
521 pr_info("rterm_efuse = %d\n", rterm_efuse);
522 return 1;
523}
524
xiang.wu1a6d6f1d2023-08-04 14:13:00 +0800525static int do_debug(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
526{
527 unsigned int enable_all = 0;
528 int pkt_op = 0;
529 unsigned int mov_val = 0;
530 unsigned char pb[28] = {0x46, 0xD0, 0x00, 0x00, 0x00, 0x00, 0x46, 0xD0,
531 0x00, 0x10, 0x21, 0xaa, 0x9b, 0x96, 0x19, 0xfc, 0x19, 0x75, 0xd5, 0x78,
532 0x10, 0x21, 0xaa, 0x9b, 0x96, 0x19, 0xfc, 0x19};
533 unsigned char hb[3] = {0x01, 0x02, 0x03};
534
535 if (argc < 1)
536 return cmd_usage(cmdtp);
537
538 if (strncmp(argv[1], "pkt", 3) == 0) {
539 enable_all = strtoul(argv[1] + 3, NULL, 16);
540 pkt_op = strtoul(argv[2], NULL, 16);
541 mov_val = strtoul(argv[3], NULL, 10);
542 pkt_send_position_change(enable_all, pkt_op, mov_val);
543 } else if (strncmp(argv[1], "w_dhdr", 6) == 0 ) {
544 hdmitx21_write_dhdr_sram();
545 } else if (strncmp(argv[1], "r_dhdr", 6) == 0 ) {
546 hdmitx21_read_dhdr_sram();
547 } else if (strncmp(argv[1], "t_avi", 4) == 0 ) {
548 printf("test send avi pkt\n");
549 hdmi_avi_infoframe_rawset(hb, pb);
550 } else if (strncmp(argv[1], "t_audio", 7) == 0 ) {
551 printf("test send audio pkt\n");
552 hdmi_audio_infoframe_rawset(hb, pb);
553 } else if (strncmp(argv[1], "t_sbtm", 6) == 0 ) {
554 printf("test send SBTM pkt\n");
555 hdmitx21_send_sbtm_pkt();
556 }
557
558 return 1;
559}
560
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800561static bool check_vic_exist(struct hdmitx_dev *hdev, enum hdmi_vic vic,
562 int count)
563{
564 struct rx_cap *rxcap = NULL;
565 int i;
566
567 rxcap = &hdev->RXCap;
568 for (i = 0; i < count; i++)
569 if (vic == rxcap->VIC[i])
570 return 1;
571
572 return 0;
573}
574
575static void disp_cap_show(struct hdmitx_dev *hdev)
576{
577 struct rx_cap *rxcap = NULL;
578 const struct hdmi_timing *timing = NULL;
579 enum hdmi_vic vic;
580 int i;
zhou.hana8e91612024-04-28 14:56:45 +0000581 enum hdmi_vic prefer_vic = HDMI_UNKNOWN;
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800582
583 if (!hdev)
584 return;
585
586 rxcap = &hdev->RXCap;
587 printf("disp_cap\n");
588 for (i = 0; i < rxcap->VIC_count && i < VIC_MAX_NUM; i++) {
589 vic = rxcap->VIC[i];
590 if (check_vic_exist(hdev, vic, i))
591 continue;
zhou.hana8e91612024-04-28 14:56:45 +0000592 prefer_vic = hdmitx21_get_prefer_vic(hdev, vic);
593 /* if mode_prefer_vic is support by RX, try 16x9 first */
594 if (prefer_vic != vic) {
595 printf("%s:prefer vic:%d exist, ignore [%d].\n", __func__, prefer_vic, vic);
596 continue;
597 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800598 timing = hdmitx21_gettiming_from_vic(vic);
599 if (timing && vic < HDMITX_VESA_OFFSET && !is_vic_over_limited_1080p(vic))
600 printf(" %s\n", timing->sname ? timing->sname : timing->name);
601 }
xiang.wu114497ab2024-02-21 14:57:05 +0800602 printf("420_cap\n");
603 for (i = 0; i < Y420_VIC_MAX_NUM; i++) {
604 vic = rxcap->y420_vic[i];
605 printf("420vic:%d\n", vic);
606 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800607}
608
609static void vesa_cap_show(struct hdmitx_dev *hdev)
610{
611}
612
613static void dc_cap_show(struct hdmitx_dev *hdev)
614{
615 enum hdmi_vic vic = HDMI_0_UNKNOWN;
616 struct rx_cap *prxcap = &hdev->RXCap;
617 const struct dv_info *dv = &hdev->RXCap.dv_info;
618
619 printf("dc_cap\n");
620 if (prxcap->dc_36bit_420)
621 printf("420,12bit\n");
622 if (prxcap->dc_30bit_420) {
623 printf("420,10bit\n");
624 printf("420,8bit\n");
625 } else {
626 vic = hdmitx_edid_get_VIC(hdev, "2160p60hz420", 0);
627 if (vic != HDMI_0_UNKNOWN) {
628 printf("420,8bit\n");
629 goto next444;
630 }
631 vic = hdmitx_edid_get_VIC(hdev, "2160p50hz420", 0);
632 if (vic != HDMI_0_UNKNOWN) {
633 printf("420,8bit\n");
634 goto next444;
635 }
636 vic = hdmitx_edid_get_VIC(hdev, "smpte60hz420", 0);
637 if (vic != HDMI_0_UNKNOWN) {
638 printf("420,8bit\n");
639 goto next444;
640 }
641 vic = hdmitx_edid_get_VIC(hdev, "smpte50hz420", 0);
642 if (vic != HDMI_0_UNKNOWN) {
643 printf("420,8bit\n");
644 goto next444;
645 }
646 }
647next444:
648 if (prxcap->native_Mode & (1 << 5)) {
649 if (prxcap->dc_y444) {
650 if (prxcap->dc_36bit || dv->sup_10b_12b_444 == 0x2)
651 printf("444,12bit\n");
652 if (prxcap->dc_30bit || dv->sup_10b_12b_444 == 0x1)
653 printf("444,10bit\n");
654 }
655 printf("444,8bit\n");
656 }
657 /* y422, not check dc */
658 if (prxcap->native_Mode & (1 << 4)) {
659 printf("422,12bit\n");
660 printf("422,10bit\n");
661 printf("422,8bit\n");
662 }
663
664 if (prxcap->dc_36bit || dv->sup_10b_12b_444 == 0x2)
665 printf("rgb,12bit\n");
666 if (prxcap->dc_30bit || dv->sup_10b_12b_444 == 0x1)
667 printf("rgb,10bit\n");
668 printf("rgb,8bit\n");
669}
670
671static void aud_cap_show(struct hdmitx_dev *hdev)
672{
673}
674
675static void hdr_cap_show(struct hdmitx_dev *hdev)
676{
677 int hdr10plugsupported = 0;
678 struct hdr_info *hdr = &hdev->RXCap.hdr_info;
xiang.wu114497ab2024-02-21 14:57:05 +0800679 const struct hdr10_plus_info *hdr10p = &hdev->RXCap.hdr_info.hdr10plus_info;
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800680
681 printf("\nhdr_cap\n");
682 if (hdr10p->ieeeoui == HDR10_PLUS_IEEE_OUI &&
683 hdr10p->application_version != 0xFF)
684 hdr10plugsupported = 1;
685 printf("HDR10Plus Supported: %d\n", hdr10plugsupported);
686 printf("HDR Static Metadata:\n");
687 printf(" Supported EOTF:\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800688 printf(" Traditional SDR: %d\n", !!(hdr->hdr_support & HDR_SUP_EOTF_SDR));
689 printf(" Traditional HDR: %d\n", !!(hdr->hdr_support & HDR_SUP_EOTF_HDR));
690 printf(" SMPTE ST 2084: %d\n", !!(hdr->hdr_support & HDR_SUP_EOTF_SMPTE_ST_2084));
691 printf(" Hybrid Log-Gamma: %d\n", !!(hdr->hdr_support & HDR_SUP_EOTF_HLG));
692 printf(" Supported SMD type1: %d\n", hdr->static_metadata_type1);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800693 printf(" Luminance Data\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800694 printf(" Max: %d\n", hdr->lumi_max);
695 printf(" Avg: %d\n", hdr->lumi_avg);
696 printf(" Min: %d\n\n", hdr->lumi_min);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800697 printf("HDR Dynamic Metadata:");
698}
699
700static void _dv_cap_show(const struct dv_info *dv)
701{
702 int i;
703
704 if (dv->ieeeoui != DV_IEEE_OUI || dv->block_flag != CORRECT) {
705 printf("The Rx don't support DolbyVision\n");
706 return;
707 }
708 printf("DolbyVision RX support list:\n");
709
710 if (dv->ver == 0) {
711 printf("VSVDB Version: V%d\n", dv->ver);
712 printf("2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
713 printf("Support mode:\n");
714 printf(" DV_RGB_444_8BIT\n");
715 if (dv->sup_yuv422_12bit)
716 printf(" DV_YCbCr_422_12BIT\n");
717 }
718 if (dv->ver == 1) {
719 printf("VSVDB Version: V%d(%d-byte)\n", dv->ver, dv->length + 1);
720 if (dv->length == 0xB) {
721 printf("2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
722 printf("Support mode:\n");
723 printf(" DV_RGB_444_8BIT\n");
724 if (dv->sup_yuv422_12bit)
725 printf(" DV_YCbCr_422_12BIT\n");
726 if (dv->low_latency == 0x01)
727 printf(" LL_YCbCr_422_12BIT\n");
728 }
729
730 if (dv->length == 0xE) {
731 printf("2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
732 printf("Support mode:\n");
733 printf(" DV_RGB_444_8BIT\n");
734 if (dv->sup_yuv422_12bit)
735 printf(" DV_YCbCr_422_12BIT\n");
736 }
737 }
738 if (dv->ver == 2) {
739 printf("VSVDB Version: V%d\n", dv->ver);
740 printf("2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
741 printf("Support mode:\n");
742 if (dv->Interface != 0x00 && dv->Interface != 0x01) {
743 printf(" DV_RGB_444_8BIT\n");
744 if (dv->sup_yuv422_12bit)
745 printf(" DV_YCbCr_422_12BIT\n");
746 }
747 printf(" LL_YCbCr_422_12BIT\n");
748 if (dv->Interface == 0x01 || dv->Interface == 0x03) {
749 if (dv->sup_10b_12b_444 == 0x1)
750 printf(" LL_RGB_444_10BIT\n");
751 if (dv->sup_10b_12b_444 == 0x2)
752 printf(" LL_RGB_444_12BIT\n");
753 }
754 }
755 printf("IEEEOUI: 0x%06x\n", dv->ieeeoui);
756 printf("VSVDB: ");
757 for (i = 0; i < (dv->length + 1); i++)
758 printf("%02x", dv->rawdata[i]);
759 printf("\n");
760}
761
762static void dv_cap_show(struct hdmitx_dev *hdev)
763{
764 const struct dv_info *dv = &hdev->RXCap.dv_info;
765
766 printf("dv_cap\n");
767 if (dv->ieeeoui != DV_IEEE_OUI) {
768 printf("The Rx don't support DolbyVision\n");
769 return;
770 }
771 _dv_cap_show(dv);
772}
773
774static void edid_cap_show(struct hdmitx_dev *hdev)
775{
776 int i;
777 struct rx_cap *prxcap = &hdev->RXCap;
778
xiang.wu114497ab2024-02-21 14:57:05 +0800779 printf("Rx EDID Parse:\n");
780 printf("Rx Manufacturer Name: %s\n", prxcap->IDManufacturerName);
781 printf("Rx Product Code: %02x%02x\n",
782 prxcap->IDProductCode[0], prxcap->IDProductCode[1]);
783 printf("Rx Serial Number: %02x%02x%02x%02x\n",
784 prxcap->IDSerialNumber[0],
785 prxcap->IDSerialNumber[1],
786 prxcap->IDSerialNumber[2],
787 prxcap->IDSerialNumber[3]);
788 printf("Rx Product Name: %s\n", prxcap->ReceiverProductName);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800789
xiang.wu114497ab2024-02-21 14:57:05 +0800790 printf("Manufacture Week: %d\n", prxcap->manufacture_week);
791 printf("Manufacture Year: %d\n", prxcap->manufacture_year + 1990);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800792
xiang.wu114497ab2024-02-21 14:57:05 +0800793 printf("Physical size(mm): %d x %d\n",
794 prxcap->physical_width, prxcap->physical_height);
795
796 printf("EDID Version: %d.%d\n",
797 prxcap->edid_version, prxcap->edid_revision);
798
799/* printf(
800 * "EDID block number: 0x%x\n", tx_comm->EDID_buf[0x7e]);
801 *
802 *
803 * printf(
804 * "Source Physical Address[a.b.c.d]: %x.%x.%x.%x\n",
805 * hdmitx_device->hdmi_info.vsdb_phy_addr.a,
806 * hdmitx_device->hdmi_info.vsdb_phy_addr.b,
807 * hdmitx_device->hdmi_info.vsdb_phy_addr.c,
808 * hdmitx_device->hdmi_info.vsdb_phy_addr.d);
809 */
810
811 // TODO native_vic2
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800812 printf("native Mode %x, VIC (native %d):\n",
xiang.wu114497ab2024-02-21 14:57:05 +0800813 prxcap->native_Mode, prxcap->native_vic);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800814
815 printf("ColorDeepSupport %x\n", prxcap->ColorDeepSupport);
816
xiang.wu114497ab2024-02-21 14:57:05 +0800817 for (i = 0; i < prxcap->VIC_count ; i++) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800818 printf("%d ", prxcap->VIC[i]);
xiang.wu114497ab2024-02-21 14:57:05 +0800819 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800820 printf("\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800821 printf("Audio {format, channel, freq, cce}\n");
822 for (i = 0; i < prxcap->AUD_count; i++) {
823 printf("{%d, %d, %x, %x}\n",
824 prxcap->RxAudioCap[i].audio_format_code,
825 prxcap->RxAudioCap[i].channel_num_max,
826 prxcap->RxAudioCap[i].freq_cc,
827 prxcap->RxAudioCap[i].cc3);
828 }
829 printf("Speaker Allocation: %x\n", prxcap->RxSpeakerAllocation);
830 printf("Vendor: 0x%x ( %s device)\n", prxcap->ieeeoui, (prxcap->ieeeoui) ? "HDMI" : "DVI");
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800831
832 printf("MaxTMDSClock1 %d MHz\n", prxcap->Max_TMDS_Clock1 * 5);
833
xiang.wu114497ab2024-02-21 14:57:05 +0800834 if (prxcap->hf_ieeeoui) {
835 printf("Vendor2: 0x%x\n",
836 prxcap->hf_ieeeoui);
837 printf("MaxTMDSClock2 %d MHz\n",
838 prxcap->Max_TMDS_Clock2 * 5);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800839 }
840
xiang.wu114497ab2024-02-21 14:57:05 +0800841 printf("MaxFRLRate: %d\n", prxcap->max_frl_rate);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800842
xiang.wu114497ab2024-02-21 14:57:05 +0800843 if (prxcap->allm)
844 printf("ALLM: %x\n", prxcap->allm);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800845
xiang.wu114497ab2024-02-21 14:57:05 +0800846 if (prxcap->cnc3)
847 printf("Game/CNC3: %x\n", prxcap->cnc3);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800848
xiang.wu114497ab2024-02-21 14:57:05 +0800849 printf("vLatency: ");
850 if (prxcap->vLatency == LATENCY_INVALID_UNKNOWN)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800851 printf(" Invalid/Unknown\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800852 else if (prxcap->vLatency == LATENCY_NOT_SUPPORT)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800853 printf(" UnSupported\n");
854 else
xiang.wu114497ab2024-02-21 14:57:05 +0800855 printf(" %d\n", prxcap->vLatency);
856
857 printf("aLatency: ");
858 if (prxcap->aLatency == LATENCY_INVALID_UNKNOWN)
859 printf(" Invalid/Unknown\n");
860 else if (prxcap->aLatency == LATENCY_NOT_SUPPORT)
861 printf(" UnSupported\n");
862 else
863 printf(" %d\n", prxcap->aLatency);
864
865 printf("i_vLatency: ");
866 if (prxcap->i_vLatency == LATENCY_INVALID_UNKNOWN)
867 printf(" Invalid/Unknown\n");
868 else if (prxcap->i_vLatency == LATENCY_NOT_SUPPORT)
869 printf(" UnSupported\n");
870 else
871 printf(" %d\n", prxcap->i_vLatency);
872
873 printf("i_aLatency: ");
874 if (prxcap->i_aLatency == LATENCY_INVALID_UNKNOWN)
875 printf(" Invalid/Unknown\n");
876 else if (prxcap->i_aLatency == LATENCY_NOT_SUPPORT)
877 printf(" UnSupported\n");
878 else
879 printf(" %d\n", prxcap->i_aLatency);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800880
881 if (prxcap->colorimetry_data)
882 printf("ColorMetry: 0x%x\n", prxcap->colorimetry_data);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800883
xiang.wu114497ab2024-02-21 14:57:05 +0800884 printf("SCDC: %x\n", prxcap->scdc_present);
885
886 printf("RR_Cap: %x\n",
887 prxcap->scdc_rr_capable);
888 printf("LTE_340M_Scramble: %x\n",
889 prxcap->lte_340mcsc_scramble);
890 /* dsc capability */
891 printf("dsc_10bpc: %d\n",
892 prxcap->dsc_10bpc);
893 printf("dsc_12bpc: %d\n",
894 prxcap->dsc_12bpc);
895 printf("dsc_16bpc: %d\n",
896 prxcap->dsc_16bpc);
897 printf("dsc_all_bpp: %d\n",
898 prxcap->dsc_all_bpp);
899 printf("dsc_native_420: %d\n",
900 prxcap->dsc_native_420);
901 printf("dsc_1p2: %d\n",
902 prxcap->dsc_1p2);
903 printf("dsc_max_slices: 0x%x(%d slices)\n",
904 prxcap->dsc_max_slices, dsc_max_slices_num[prxcap->dsc_max_slices]);
905 printf("dsc_max_frl_rate: 0x%x\n",
906 prxcap->dsc_max_frl_rate);
907 printf("dsc_total_chunk_bytes: 0x%x\n",
908 prxcap->dsc_total_chunk_bytes);
909 if (prxcap->dv_info.ieeeoui == DOVI_IEEEOUI)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800910 printf(" DolbyVision%d", prxcap->dv_info.ver);
xiang.wu114497ab2024-02-21 14:57:05 +0800911
912 if (prxcap->hdr_info2.hdr_support)
913 printf(" HDR/%d",
914 prxcap->hdr_info2.hdr_support);
915 if (prxcap->hdr_info.sbtm_info.sbtm_support)
916 printf(" SBTM");
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800917 if (prxcap->dc_y444 || prxcap->dc_30bit || prxcap->dc_30bit_420)
918 printf(" DeepColor");
919 printf("\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800920 printf("additional_vsif_num: %d\n", prxcap->additional_vsif_num);
921 printf("ifdb_present: %d\n", prxcap->ifdb_present);
922 /* for checkvalue which maybe used by application to adjust
923 * whether edid is changed
924 */
925 printf("checkvalue: %s\n", prxcap->hdmichecksum);
926
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800927}
928
929static int do_info(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
930{
931 struct hdmitx_dev *hdev = get_hdmitx21_device();
932 struct hdmi_format_para *para;
933
934 if (!hdev) {
935 pr_info("null hdmitx dev\n");
936 return CMD_RET_FAILURE;
937 }
938 if (!hdev->para) {
939 printf("null hdmitx para\n");
940 return CMD_RET_FAILURE;
941 }
942
943 para = hdev->para;
944 printf("current mode %s vic %d\n", para->timing.name, hdev->vic);
945 printf("cd%d cs%d cr%d\n", para->cd, para->cs, para->cr);
946 printf("enc_idx %d\n", hdev->enc_idx);
947 printf("frac_rate: %d\n", hdev->frac_rate_policy);
948 printf("Rx EDID info\n");
949 dump_full_edid(hdev->rawedid);
950 disp_cap_show(hdev);
951 vesa_cap_show(hdev);
952 aud_cap_show(hdev);
953 hdr_cap_show(hdev);
954 dv_cap_show(hdev);
955 dc_cap_show(hdev);
956 edid_cap_show(hdev);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800957 printf("dsc policy: %d, enable: %d\n", hdev->dsc_policy, hdev->dsc_en);
958 printf("frl_rate: %d\n", hdev->frl_rate);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800959 return 1;
960}
961
962static int xtochar(int num, char *checksum)
963{
964 struct hdmitx_dev *hdev = get_hdmitx21_device();
965
966 if (((hdev->rawedid[num] >> 4) & 0xf) <= 9)
967 checksum[0] = ((hdev->rawedid[num] >> 4) & 0xf) + '0';
968 else
969 checksum[0] = ((hdev->rawedid[num] >> 4) & 0xf) - 10 + 'a';
970
971 if ((hdev->rawedid[num] & 0xf) <= 9)
972 checksum[1] = (hdev->rawedid[num] & 0xf) + '0';
973 else
974 checksum[1] = (hdev->rawedid[num] & 0xf) - 10 + 'a';
975
976 return 0;
977}
978
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800979/* hdr_priority definition:
980 * strategy1: bit[3:0]
981 * 0: original cap
982 * 1: disable dolby vision cap
983 * 2: disable dolby vision and hdr/hlg cap
984 * strategy2:
985 * bit4: 1: disable dv 0:enable dv
986 * bit5: 1: disable hdr10/hdr10+ 0: enable hdr10/hdr10+
987 * bit6: 1: disable hlg 0: enable hlg
988 * bit28-bit31 choose strategy: bit[31:28]
989 * 0: strategy1
990 * 1: strategy2
991 */
992
993/* for uboot, there is no need to dynamically change the hdr_priority as
994 * kernel. So below functions only implement the disable_xxx_info() function,
995 * and leave the enable_xxx_info as blank
996 */
997
998/* dv_info */
999static void enable_dv_info(struct dv_info *des, const struct dv_info *src)
1000{
1001 if (!des || !src)
1002 return;
1003}
1004
1005static void disable_dv_info(struct dv_info *des)
1006{
1007 if (!des)
1008 return;
1009
1010 memset(des, 0, sizeof(*des));
1011}
1012
1013/* hdr10 */
1014static void enable_hdr10_info(struct hdr_info *des, const struct hdr_info *src)
1015{
1016 if (!des || !src)
1017 return;
1018}
1019
1020static void disable_hdr10_info(struct hdr_info *des)
1021{
1022 if (!des)
1023 return;
1024
xiang.wu114497ab2024-02-21 14:57:05 +08001025 des->hdr_support = des->hdr_support & 0xB;
1026 des->static_metadata_type1 = 0;
1027 des->lumi_max = 0;
1028 des->lumi_avg = 0;
1029 des->lumi_min = 0;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001030}
1031
1032/* hdr10plus */
1033static void enable_hdr10p_info(struct hdr10_plus_info *des, const struct hdr10_plus_info *src)
1034{
1035 if (!des || !src)
1036 return;
1037}
1038
1039static void disable_hdr10p_info(struct hdr10_plus_info *des)
1040{
1041 if (!des)
1042 return;
1043
1044 memset(des, 0, sizeof(*des));
1045}
1046
1047/* hlg */
1048static void enable_hlg_info(struct hdr_info *des, const struct hdr_info *src)
1049{
1050 if (!des || !src)
1051 return;
1052}
1053
1054static void disable_hlg_info(struct hdr_info *des)
1055{
1056 if (!des)
1057 return;
1058
xiang.wu114497ab2024-02-21 14:57:05 +08001059 des->hdr_support = des->hdr_support & 0x7;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001060}
1061
1062static void enable_all_hdr_info(struct rx_cap *prxcap)
1063{
1064 if (!prxcap)
1065 return;
1066}
1067
1068static void update_hdr_strategy1(struct rx_cap *prxcap, u32 strategy)
1069{
1070 if (!prxcap)
1071 return;
1072
1073 switch (strategy) {
1074 case 0:
1075 enable_all_hdr_info(prxcap);
1076 break;
1077 case 1:
1078 disable_dv_info(&prxcap->dv_info);
1079 break;
1080 case 2:
1081 disable_dv_info(&prxcap->dv_info);
1082 disable_hdr10_info(&prxcap->hdr_info);
xiang.wu114497ab2024-02-21 14:57:05 +08001083 disable_hdr10p_info(&prxcap->hdr_info.hdr10plus_info);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001084 disable_hlg_info(&prxcap->hdr_info);
1085 break;
1086 default:
1087 break;
1088 }
1089}
1090
1091static void update_hdr_strategy2(struct rx_cap *prxcap, u32 strategy)
1092{
1093 if (!prxcap)
1094 return;
1095
1096 /* bit4: 1 disable dv 0 enable dv */
1097 if (strategy & BIT(4))
1098 disable_dv_info(&prxcap->dv_info);
1099 else
1100 enable_dv_info(&prxcap->dv_info, NULL);
1101 /* bit5: 1 disable hdr10/hdr10+ 0 enable hdr10/hdr10+ */
1102 if (strategy & BIT(5)) {
1103 disable_hdr10_info(&prxcap->hdr_info);
xiang.wu114497ab2024-02-21 14:57:05 +08001104 disable_hdr10p_info(&prxcap->hdr_info.hdr10plus_info);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001105 } else {
1106 enable_hdr10_info(&prxcap->hdr_info, NULL);
xiang.wu114497ab2024-02-21 14:57:05 +08001107 enable_hdr10p_info(&prxcap->hdr_info.hdr10plus_info, NULL);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001108 }
1109 /* bit6: 1 disable hlg 0 enable hlg */
1110 if (strategy & BIT(6))
1111 disable_hlg_info(&prxcap->hdr_info);
1112 else
1113 enable_hlg_info(&prxcap->hdr_info, NULL);
1114}
1115
1116static int hdmitx_set_hdr_priority(struct rx_cap *prxcap, u32 hdr_priority)
1117{
1118 u32 choose = 0;
1119 u32 strategy = 0;
1120
1121 if (!prxcap)
1122 return -1;
1123
1124 printf("%s, set hdr_prio: %u\n", __func__, hdr_priority);
1125 /* choose strategy: bit[31:28] */
1126 choose = (hdr_priority >> 28) & 0xf;
1127 switch (choose) {
1128 case 0:
1129 strategy = hdr_priority & 0xf;
1130 update_hdr_strategy1(prxcap, strategy);
1131 break;
1132 case 1:
1133 strategy = hdr_priority & 0xf0;
1134 update_hdr_strategy2(prxcap, strategy);
1135 break;
1136 default:
1137 break;
1138 }
1139 return 0;
1140}
1141
xiang.wu100ee50f2024-05-21 19:39:45 +08001142void hdmitx_update_dv_strategy_info(struct dv_info *dv)
1143{
1144 if (dv->ver == 0) {
1145 if (dv->length == 0x19)
1146 dv->support_DV_RGB_444_8BIT = 1;
1147 }
1148
1149 if (dv->ver == 1) {
1150 if (dv->length == 0x0B) {
1151 dv->support_DV_RGB_444_8BIT = 1;
1152 if (dv->low_latency == 0x01)
1153 dv->support_LL_YCbCr_422_12BIT = 1;
1154 } else if (dv->length == 0x0E) {
1155 dv->support_DV_RGB_444_8BIT = 1;
1156 }
1157 }
1158
1159 if (dv->ver == 2) {
1160 if (dv->length >= 0x0B) {
1161 if (dv->Interface != 0x00 && dv->Interface != 0x01)
1162 dv->support_DV_RGB_444_8BIT = 1;
1163 dv->support_LL_YCbCr_422_12BIT = 1;
1164 if (dv->Interface == 0x01 || dv->Interface == 0x03) {
1165 if (dv->sup_10b_12b_444 == 0x1)
1166 dv->support_LL_RGB_444_10BIT = 1;
1167 if (dv->sup_10b_12b_444 == 0x2)
1168 dv->support_LL_RGB_444_12BIT = 1;
1169 }
1170 }
1171 }
1172}
1173
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001174static void get_parse_edid_data(struct hdmitx_dev *hdev)
1175{
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001176 int hdr_priority = get_hdr_strategy_priority();
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001177
1178 hdev->hwop.read_edid(hdev->rawedid);
1179
ruofei.zhao4a2ec0c2023-10-31 19:24:41 +08001180 /* dump edid raw data */
1181 dump_full_edid(hdev->rawedid);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001182
1183 /* parse edid data */
xiang.wu114497ab2024-02-21 14:57:05 +08001184 hdmitx_edid_parse(&hdev->RXCap, hdev->rawedid);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001185
xiang.wu100ee50f2024-05-21 19:39:45 +08001186 /* Update the member variables used by the dv running strategy */
1187 hdmitx_update_dv_strategy_info(&hdev->RXCap.dv_info);
1188 hdmitx_update_dv_strategy_info(&hdev->RXCap.dv_info2);
1189
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001190 if (hdr_priority == -1)
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001191 return;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001192 hdmitx_set_hdr_priority(&hdev->RXCap, hdr_priority);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001193}
1194
1195/* policy process: to find the output mode/attr/dv_type */
1196void scene_process(struct hdmitx_dev *hdev,
1197 struct scene_output_info *scene_output_info)
1198{
1199 struct input_hdmi_data hdmidata;
hang cheng517b28d2024-04-24 21:20:38 +08001200 int dv_support = 0;
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001201
1202 if (!hdev || !scene_output_info)
1203 return;
1204 /* 1.read dolby vision mode from prop(maybe need to env) */
1205 memset(&hdmidata, 0, sizeof(struct input_hdmi_data));
1206 get_hdmi_data(hdev, &hdmidata);
1207
1208 /* 2. dolby vision scene process */
1209 /* only for tv support dv and box enable dv */
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001210 if (is_dv_preference(hdev)) {
hang cheng517b28d2024-04-24 21:20:38 +08001211 dv_support = dolbyvision_scene_process(&hdmidata, scene_output_info);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001212 } else if (is_dolby_enabled()) {
1213 /* for enable dolby vision core when
1214 * first boot connecting non dv tv
1215 * NOTE: let systemcontrol to enable DV core
1216 */
1217 /* scene_output_info->final_dv_type = DOLBY_VISION_ENABLE; */
1218 } else {
1219 /* for UI disable dolby vision core and boot keep the status
1220 * NOTE: TBD if need to disable DV here
1221 */
1222 /* scene_output_info->final_dv_type = DOLBY_VISION_DISABLE; */
1223 }
hang cheng517b28d2024-04-24 21:20:38 +08001224 /* 3.hdr/sdr scene process */
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001225 /* decide final display mode and deepcolor */
hang cheng517b28d2024-04-24 21:20:38 +08001226 if (is_dv_preference(hdev) && dv_support == 0) {
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001227 /* do nothing
1228 * already done above, just sync with sysctrl
1229 */
hang cheng517b28d2024-04-24 21:20:38 +08001230 } else if (is_hdr_preference(hdev) || dv_support != 0) {
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001231 hdr_scene_process(&hdmidata, scene_output_info);
1232 } else {
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001233 sdr_scene_process(&hdmidata, scene_output_info);
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001234 }
1235 /* not find outputmode and use default mode */
1236 if (strlen(scene_output_info->final_displaymode) == 0)
1237 strcpy(scene_output_info->final_displaymode, DEFAULT_HDMI_MODE);
1238 /* not find color space and use default mode */
1239 if (!strstr(scene_output_info->final_deepcolor, "bit"))
1240 strcpy(scene_output_info->final_deepcolor, DEFAULT_COLOR_FORMAT);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001241}
1242
1243static int do_get_parse_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1244{
1245 struct hdmitx_dev *hdev = get_hdmitx21_device();
1246 unsigned char *edid = hdev->rawedid;
1247 unsigned char *store_checkvalue;
1248
xiang.wu114497ab2024-02-21 14:57:05 +08001249 memset(edid, 0, EDID_BLK_SIZE * EDID_MAX_BLOCK);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001250 unsigned int i;
1251 unsigned int checkvalue[4];
1252 unsigned int checkvalue1;
1253 unsigned int checkvalue2;
1254 char checksum[11];
1255 unsigned char def_cksum[] = {'0', 'x', '0', '0', '0', '0', '0', '0', '0', '0', '\0'};
1256 char *hdmimode;
1257 char *colorattribute;
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001258 int user_dv_mode;
1259 char *last_output_mode;
1260 char *last_colorattribute;
1261 int last_dv_status;
1262 bool over_write = false;
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001263 char dv_type[2] = {0};
1264 struct scene_output_info scene_output_info;
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001265 struct hdmi_format_para *para = NULL;
1266 bool mode_support = false;
1267 /* hdmi_mode / colorattribute may be null or "none".
1268 * if either is null or "none", it means user not
1269 * selected manually, and need to select the best
1270 * mode or colorattribute by policy
1271 */
1272 bool no_manual_output = false;
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001273
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001274 if (!hdev->hpd_state) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001275 printf("HDMI HPD low, no need parse EDID\n");
1276 return 1;
1277 }
1278 memset(&scene_output_info, 0, sizeof(struct scene_output_info));
1279
1280 get_parse_edid_data(hdev);
1281
1282 /* check if the tv has changed or anything wrong */
1283 store_checkvalue = (unsigned char *)env_get("hdmichecksum");
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001284 /* get user selected output mode/color */
1285 colorattribute = env_get("user_colorattribute");
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001286 hdmimode = env_get("hdmimode");
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001287 user_dv_mode = get_ubootenv_dv_type();
1288
1289 last_output_mode = env_get("outputmode");
1290 last_colorattribute = env_get("colorattribute");
1291 last_dv_status = get_ubootenv_dv_status();
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001292 if (!store_checkvalue)
1293 store_checkvalue = def_cksum;
1294
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001295 printf("read hdmichecksum: %s, user hdmimode: %s, colorattribute: %s, dv_type: %d\n",
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001296 store_checkvalue, hdmimode ? hdmimode : "null",
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001297 colorattribute ? colorattribute : "null", user_dv_mode);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001298
1299 for (i = 0; i < 4; i++) {
1300 if (('0' <= store_checkvalue[i * 2 + 2]) && (store_checkvalue[i * 2 + 2] <= '9'))
1301 checkvalue1 = store_checkvalue[i * 2 + 2] - '0';
1302 else
1303 checkvalue1 = store_checkvalue[i * 2 + 2] - 'W';
1304 if (('0' <= store_checkvalue[i * 2 + 3]) && (store_checkvalue[i * 2 + 3] <= '9'))
1305 checkvalue2 = store_checkvalue[i * 2 + 3] - '0';
1306 else
1307 checkvalue2 = store_checkvalue[i * 2 + 3] - 'W';
1308 checkvalue[i] = checkvalue1 * 16 + checkvalue2;
1309 }
1310
1311 if (checkvalue[0] != hdev->rawedid[0x7f] ||
1312 checkvalue[1] != hdev->rawedid[0xff] ||
1313 checkvalue[2] != hdev->rawedid[0x17f] ||
1314 checkvalue[3] != hdev->rawedid[0x1ff]) {
1315 hdev->RXCap.edid_changed = 1;
1316
1317 checksum[0] = '0';
1318 checksum[1] = 'x';
1319 for (i = 0; i < 4; i++)
1320 xtochar(0x80 * i + 0x7f, &checksum[2 * i + 2]);
1321 checksum[10] = '\0';
xiang.wu114497ab2024-02-21 14:57:05 +08001322 memcpy(hdev->RXCap.hdmichecksum, checksum, 10);
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001323 printf("TV has changed, now crc: %s\n", checksum);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001324 } else {
xiang.wu114497ab2024-02-21 14:57:05 +08001325 memcpy(hdev->RXCap.hdmichecksum, store_checkvalue, 10);
1326 printf("TV is same, checksum: %s\n", hdev->RXCap.hdmichecksum);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001327 }
1328
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001329 /* check user have selected both mode/color or not */
1330 if (!hdmimode || !strcmp(hdmimode, "none") ||
1331 !colorattribute || !strcmp(colorattribute, "none"))
1332 no_manual_output = true;
1333 else
1334 no_manual_output = false;
1335
1336 if (!no_manual_output) {
1337 /* check current user selected mode + color support or not */
1338 para = hdmitx21_get_fmtpara(hdmimode, colorattribute);
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001339 if (hdmitx_edid_check_valid_mode(hdev, para)) {
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001340 mode_support = true;
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001341 } else {
1342 printf("saved output mode not supported!\n");
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001343 mode_support = false;
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001344 }
1345
1346 /* if user selected mode/color/dv type which saved in ubootenv of
1347 * hdmimode/user_colorattribute/user_prefer_dv_type are different
1348 * with last actual output mode/color/dv type which saved in
1349 * ubootenv of outputmode/colorattribute/dolby_status, then it means
1350 * that the user selected format is over-writen by policy(for example:
1351 * firstly user has selected HDR priority to HDR, and select color
1352 * to rgb,12bit(now the "user_colorattribute" env will be "rgb,12bit"),
1353 * but then it selected HDR priority to DV, the actual output color
1354 * will be "444,8bit" or "422,12bit" according to dv type, and
1355 * the ubootenv "colorattribute" will be "444,8bit" or "422,12bit"),
1356 * then uboot should use the policy to select the output format,
1357 * otherwise, uboot use hdmimode/user_colorattribute/user_prefer_dv_type
1358 * env, while system use outputmode/colorattribute/dolby_status env,
1359 * there will be always a mode change during bootup
1360 */
1361 if (mode_support) {
1362 /* note that for T7 multi-display, it may store panel in
1363 * "outputmode" env, and will always run uboot policy
1364 */
1365 if (!last_output_mode || strcmp(hdmimode, last_output_mode))
1366 over_write = true;
1367 else if (!last_colorattribute ||
1368 strcmp(colorattribute, last_colorattribute))
1369 over_write = true;
1370 else if (user_dv_mode != last_dv_status)
1371 over_write = true;
1372 else
1373 over_write = false;
1374
1375 if (over_write)
1376 printf("last output_mode:%s, colorattribute:%s, dolby_status:%d\n",
1377 last_output_mode ? last_output_mode : "null",
1378 last_colorattribute ? last_colorattribute : "null",
1379 last_dv_status);
1380 }
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001381 }
xiang.wu1dba66a02024-05-28 19:53:01 +08001382 /* When outputting frl mode, if frl training fails under uboot,
1383 * in order to ensure that it is displayed under uboot, change
1384 * to the default TMDS mode for output display. systemctrl
1385 * maintains the original 8k policy. After the subsequent systermctrl
1386 * starts running, if it is checked that the current output is not the
1387 * original frl mode, it will switch to the original frl mode.
1388 */
1389 if (hdev->frl_train_fail_flag) {
1390 save_default_720p();
1391 } else if (hdev->RXCap.edid_changed || no_manual_output || !mode_support || over_write) {
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001392 /* 4 cases need to decide output by uboot mode select policy:
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001393 * 1.TV changed
1394 * 2.either hdmimode or colorattribute is NULL or "none",
1395 * which means that user have not selected mode or colorattribute,
1396 * and need to select the auto best mode or best colorattribute.
1397 * 3.user selected mode not supportted by uboot (probably
1398 * means mode select policy or edid parse between sysctrl and
1399 * uboot have some gap), then need to find proper output mode
1400 * with uboot policy.
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001401 * 4.user selected mode is over writen by system policy
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001402 */
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001403 /* find proper mode if EDID changed */
1404 scene_process(hdev, &scene_output_info);
xiang.wu114497ab2024-02-21 14:57:05 +08001405 env_set("hdmichecksum", hdev->RXCap.hdmichecksum);
1406 if (hdmitx_edid_check_data_valid(0, hdev->rawedid)) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001407 /* SWPL-34712: if EDID parsing error case, not save env,
1408 * only output default mode(480p,RGB,8bit). after
1409 * EDID read OK, systemcontrol will recover the hdmi
1410 * mode from env, to avoid keep the default hdmi output
1411 */
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001412 memcpy(sel_hdmimode, scene_output_info.final_displaymode,
1413 sizeof(scene_output_info.final_displaymode));
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001414 if (is_hdmi_mode(env_get("outputmode"))) {
1415 env_set("outputmode",
1416 scene_output_info.final_displaymode);
1417 } else if (is_hdmi_mode(env_get("outputmode2"))) {
1418 env_set("outputmode2",
1419 scene_output_info.final_displaymode);
1420 } else if (is_hdmi_mode(env_get("outputmode3"))) {
1421 env_set("outputmode3",
1422 scene_output_info.final_displaymode);
1423 }
1424 env_set("colorattribute",
1425 scene_output_info.final_deepcolor);
1426 /* if change from DV TV to HDR/SDR TV, don't change
1427 * DV status to disabled, as DV core need to be enabled.
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001428 * that's to say connect DV TV & output DV-> power down box ->
1429 * connect HDR/SDR TV -> power on box, the dolby_status
1430 * will keep the same as that when connect DV TV under follow sink.
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001431 */
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001432 if (scene_output_info.final_dv_type != get_ubootenv_dv_status() &&
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001433 scene_output_info.final_dv_type != DOLBY_VISION_DISABLE) {
1434 sprintf(dv_type, "%d", scene_output_info.final_dv_type);
1435 env_set("dolby_status", dv_type);
1436 /* according to the policy of systemcontrol,
1437 * if current DV mode is not supported by TV
1438 * EDID, DV type maybe changed to one witch
1439 * TV support, and need VPP/DV module to
1440 * update new DV output mode.
1441 */
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001442 printf("update dolby_status: %d\n",
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001443 scene_output_info.final_dv_type);
1444 }
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001445 } else {
1446 save_default_720p();
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001447 }
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001448 printf("update outputmode: %s\n", sel_hdmimode);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001449 printf("update colorattribute: %s\n", env_get("colorattribute"));
1450 printf("update hdmichecksum: %s\n", env_get("hdmichecksum"));
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001451 } else {
1452 memset(sel_hdmimode, 0, sizeof(sel_hdmimode));
1453 memcpy(sel_hdmimode, hdmimode, strlen(hdmimode));
1454 if (is_hdmi_mode(env_get("outputmode")))
1455 env_set("outputmode", hdmimode);
1456 else if (is_hdmi_mode(env_get("outputmode2")))
1457 env_set("outputmode2", hdmimode);
1458 else if (is_hdmi_mode(env_get("outputmode3")))
1459 env_set("outputmode3", hdmimode);
1460 env_set("colorattribute", colorattribute);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001461 }
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001462 env_set("save_outputmode", sel_hdmimode);
1463 /* ubootenv dolby_status is used for is_dv_preference() decision,
1464 * system_control save current dv output status in it.
1465 * it will be used by dv module later to decide DV output later.
1466 * if currently adaptive hdr, then we should set dolby_status to
1467 * 0, so that DV module won't enable DV.
1468 */
1469 if (get_hdr_policy() == 1)
1470 env_set("dolby_status", 0);
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001471 hdev->para = hdmitx21_get_fmtpara(sel_hdmimode, env_get("colorattribute"));
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001472 hdev->vic = hdev->para->timing.vic;
1473 hdmitx_mask_rx_info(hdev);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001474 hdmitx21_select_frl(hdev);
1475 return 0;
1476}
1477
1478static int do_dsc_policy(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1479{
1480 struct hdmitx_dev *hdev = get_hdmitx21_device();
1481
1482 if (argc < 1)
1483 return cmd_usage(cmdtp);
1484
1485 if (strcmp(argv[1], "0") == 0)
1486 hdev->dsc_policy = 0;
1487 else if (strcmp(argv[1], "1") == 0)
1488 hdev->dsc_policy = 1;
1489 else if (strcmp(argv[1], "2") == 0)
1490 hdev->dsc_policy = 2;
1491 else if (strcmp(argv[1], "3") == 0)
1492 hdev->dsc_policy = 3;
1493 else if (strcmp(argv[1], "4") == 0)
1494 hdev->dsc_policy = 4;
1495 else
1496 printf("note: please set dsc policy as 0~4\n");
1497 if (hdev->dsc_policy <= 4)
1498 printf("use dsc policy: %d\n", hdev->dsc_policy);
1499
1500 return CMD_RET_SUCCESS;
1501}
1502
1503static int do_manual_frl_rate(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1504{
1505 struct hdmitx_dev *hdev = get_hdmitx21_device();
1506 unsigned int temp = 0;
1507 char *ptr;
1508
1509 /* if rx don't support FRL, return */
1510 if (!hdev->RXCap.max_frl_rate) {
1511 printf("rx not support FRL\n");
1512 return 0;
1513 }
1514
1515 temp = strtoul(argv[1], &ptr, 16);
1516 /* forced FRL rate setting */
1517 if (temp <= 6) {
1518 hdev->manual_frl_rate = temp;
1519 pr_info("force set frl_rate as %d\n", hdev->manual_frl_rate);
1520 } else {
1521 pr_info("error: should set frl_rate in 0 ~ 6\n");
1522 }
1523 if (hdev->manual_frl_rate > hdev->RXCap.max_frl_rate)
1524 pr_info("warning: larger than rx max_frl_rate %d\n", hdev->RXCap.max_frl_rate);
1525 return 0;
1526}
1527
1528static int do_manual_dfm_type(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1529{
1530 struct hdmitx_dev *hdev = get_hdmitx21_device();
1531 unsigned int temp = 0;
1532 char *ptr;
1533
1534 temp = strtoul(argv[1], &ptr, 10);
1535 /* forced dfm_type setting */
1536 if (temp <= 2) {
1537 hdev->dfm_type = temp;
1538 pr_info("force set dfm_type as %d\n", hdev->dfm_type);
1539 } else {
1540 pr_info("error: should set frl_rate in 0 ~ 2\n");
1541 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001542 return 0;
1543}
1544
Wenjie Qiao77833902023-12-18 19:01:59 +08001545#ifdef CONFIG_EFUSE_OBJ_API
1546static int do_efuse_show(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1547{
1548 struct hdmitx_dev *hdev = get_hdmitx21_device();
1549
1550 get_hdmi_efuse(hdev);
1551 pr_info("FEAT_DISABLE_HDMI_60HZ = %d\n", hdev->efuse_dis_hdmi_4k60);
1552 pr_info("FEAT_DISABLE_OUTPUT_4K = %d\n", hdev->efuse_dis_output_4k);
1553 pr_info("FEAT_DISABLE_HDCP_TX_22 = %d\n", hdev->efuse_dis_hdcp_tx22);
1554 pr_info("FEAT_DISABLE_HDMI_TX_3D = %d\n", hdev->efuse_dis_hdmi_tx3d);
1555 pr_info("FEAT_DISABLE_HDMI = %d\n", hdev->efuse_dis_hdcp_tx14);
1556
1557 return 0;
1558}
1559#endif
1560
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001561static cmd_tbl_t cmd_hdmi_sub[] = {
1562 U_BOOT_CMD_MKENT(hpd, 1, 1, do_hpd_detect, "", ""),
1563 U_BOOT_CMD_MKENT(edid, 3, 1, do_edid, "", ""),
1564 U_BOOT_CMD_MKENT(rx_det, 1, 1, do_rx_det, "", ""),
1565 U_BOOT_CMD_MKENT(output, 3, 1, do_output, "", ""),
1566 U_BOOT_CMD_MKENT(clkmsr, 3, 1, do_clkmsr, "", ""),
1567 U_BOOT_CMD_MKENT(blank, 3, 1, do_blank, "", ""),
1568 U_BOOT_CMD_MKENT(off, 1, 1, do_off, "", ""),
1569 U_BOOT_CMD_MKENT(dump, 1, 1, do_dump, "", ""),
1570 U_BOOT_CMD_MKENT(info, 1, 1, do_info, "", ""),
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001571 U_BOOT_CMD_MKENT(reg, 3, 1, do_reg, "", ""),
1572 U_BOOT_CMD_MKENT(get_parse_edid, 1, 1, do_get_parse_edid, "", ""),
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001573 U_BOOT_CMD_MKENT(dsc_policy, 1, 1, do_dsc_policy, "", ""),
1574 U_BOOT_CMD_MKENT(frl_rate, 1, 1, do_manual_frl_rate, "", ""),
1575 U_BOOT_CMD_MKENT(dfm_type, 1, 1, do_manual_dfm_type, "", ""),
Wenjie Qiao77833902023-12-18 19:01:59 +08001576#ifdef CONFIG_EFUSE_OBJ_API
1577 U_BOOT_CMD_MKENT(efuse, 1, 1, do_efuse_show, "", ""),
1578#endif
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001579 U_BOOT_CMD_MKENT(pbist, 3, 1, do_pbist, "", ""),
1580 U_BOOT_CMD_MKENT(debug, 3, 1, do_debug, "", ""),
xiang.wu1492f3642024-01-08 14:06:40 +08001581 U_BOOT_CMD_MKENT(s7_clk_config, 3, 1, do_s7_clk_config, "", ""),
xiang.wu114497ab2024-02-21 14:57:05 +08001582 U_BOOT_CMD_MKENT(get_rterm, 3, 1, get_rterm, "", ""),
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001583};
1584
1585static int do_hdmitx(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1586{
1587 cmd_tbl_t *c;
1588
1589 if (argc < 2)
1590 return cmd_usage(cmdtp);
1591
1592 argc--;
1593 argv++;
1594
1595 c = find_cmd_tbl(argv[0], &cmd_hdmi_sub[0], ARRAY_SIZE(cmd_hdmi_sub));
1596
1597 if (c)
1598 return c->cmd(cmdtp, flag, argc, argv);
1599 else
1600 return cmd_usage(cmdtp);
1601}
1602
1603U_BOOT_CMD(hdmitx, CONFIG_SYS_MAXARGS, 0, do_hdmitx,
1604 "HDMITX sub-system",
1605 "hdmitx version:20200618\n"
1606 "hdmitx hpd\n"
1607 " Detect hdmi rx plug-in\n"
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001608 "hdmitx output [list | FORMAT | bist PATTERN]\n"
1609 " list: list support formats\n"
1610 " FORMAT can be 720p60/50hz, 1080i60/50hz, 1080p60hz, etc\n"
1611 " extend with 8bits/10bits, y444/y422/y420/rgb\n"
1612 " such as 2160p60hz,10bits,y420\n"
1613 " PATTERN: can be as: line, dot, off, or 1920(width)\n"
1614 "hdmitx blank [0|1]\n"
1615 " 1: output blank 0: output normal\n"
1616 "hdmitx clkmsr\n"
1617 " show hdmitx clocks\n"
1618 "hdmitx off\n"
1619 " Turn off hdmitx output\n"
1620 "hdmitx info\n"
1621 " current mode info\n"
1622 "hdmitx rx_det\n"
1623 " Auto detect if RX is FBC and set outputmode\n"
1624);
1625
1626struct hdr_info *hdmitx_get_rx_hdr_info(void)
1627{
1628 struct hdmitx_dev *hdev = get_hdmitx21_device();
1629
1630 return &hdev->RXCap.hdr_info;
1631}
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001632
1633static int do_list_dsc_mode(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1634{
1635#ifdef CONFIG_AML_DSC_ENC
1636 dsc_enc_cap_show();
1637#endif
1638 return 0;
1639}
1640
1641static int do_dsc_debug(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1642{
1643#ifdef CONFIG_AML_DSC_ENC
1644 dsc_debug(argc - 1, argv + 1);
1645#endif
1646 return 0;
1647}
1648
1649static cmd_tbl_t cmd_dsc_sub[] = {
1650 U_BOOT_CMD_MKENT(list_mode, 1, 1, do_list_dsc_mode, "", ""),
1651 U_BOOT_CMD_MKENT(dbg, 20, 1, do_dsc_debug, "", ""),
1652};
1653
1654static int do_dsc_enc(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1655{
1656 cmd_tbl_t *c;
1657
1658 if (argc < 2)
1659 return cmd_usage(cmdtp);
1660
1661 argc--;
1662 argv++;
1663
1664 c = find_cmd_tbl(argv[0], &cmd_dsc_sub[0], ARRAY_SIZE(cmd_dsc_sub));
1665
1666 if (c)
1667 return c->cmd(cmdtp, flag, argc, argv);
1668 else
1669 return cmd_usage(cmdtp);
1670}
1671
1672U_BOOT_CMD(dsc, CONFIG_SYS_MAXARGS, 0, do_dsc_enc,
1673 "dsc cmd",
1674 "dsc help function\n"
1675 "dsc dbg state\n"
1676 " dump dsc status\n"
1677 "dsc dbg dump_reg\n"
1678 " dump dsc registers and venc registers\n"
1679 "dsc dbg read addr\n"
1680 " read dsc asic register\n"
1681 "dsc dbg write addr value\n"
1682 " write dsc asic register\n"
1683 "dsc dbg rst_dsc\n"
1684 " reset dsc enc\n"
1685 "dsc list_mode\n"
1686 " show supported dsc encode mode list\n"
1687);
1688