blob: 8311fa621bfb236be34227d1adc7daf0cc8f014f [file] [log] [blame]
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
4 */
5
6#include <common.h>
7#include <command.h>
8#include <env.h>
9#include <malloc.h>
10#include <asm/byteorder.h>
11#include <amlogic/clk_measure.h>
12#include <amlogic/media/vout/hdmitx21/hdmitx.h>
Wenjie Qiao389d3ea2023-05-25 16:07:03 +080013#include <linux/delay.h>
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +080014#include <image.h>
Wenjie Qiao8a73a562023-02-23 18:37:14 +080015#include <amlogic/media/dv/dolby_vision.h>
16#include <linux/libfdt_env.h>
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +080017#include <amlogic/media/vout/dsc.h>
xiang.wu114497ab2024-02-21 14:57:05 +080018#include <amlogic/media/vout/aml_vinfo.h>
19#include <linux/arm-smccc.h>
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +080020#include <linux/compat.h>
xiang.wu1dc0df262024-07-22 19:34:22 +080021#include "../../drivers/amlogic/media/vout/hdmitx/hdmitx_common/hdmitx_check_valid.h"
xiang.wu18cf0cd12024-06-13 15:27:52 +080022#include "../../drivers/amlogic/media/vout/hdmitx/hdmitx_common/hdmitx_policy_setting.h"
xiang.wu15613f462024-09-04 17:42:04 +080023#include "../../drivers/amlogic/media/vout/hdmitx/hdmitx_common/hdmitx_compliance.h"
Wenjie Qiao8a73a562023-02-23 18:37:14 +080024
25static unsigned char edid_raw_buf[512] = {0};
lizhi.hu506ddfa2024-07-10 21:35:41 +080026
27/*
28 * there may be outputmode/2/3 when in multi-display case,
Wenjie Qiao389d3ea2023-05-25 16:07:03 +080029 * sel_hdmimode is used to save the selected hdmi mode
30 */
xiang.wu18cf0cd12024-06-13 15:27:52 +080031static char sel_hdmimode[MESON_MODE_LEN] = {0};
Wenjie Qiao8a73a562023-02-23 18:37:14 +080032
33static void dump_full_edid(const unsigned char *buf)
34{
35 int i;
36 int blk_no;
37
38 if (!buf)
39 return;
40 blk_no = buf[126] + 1;
41 if (blk_no > 4)
42 blk_no = 4;
Wenjie Qiao389d3ea2023-05-25 16:07:03 +080043
44 if (blk_no == 2)
45 if (buf[128 + 4] == 0xe2 && buf[128 + 5] == 0x78)
46 blk_no = buf[128 + 6] + 1;
xiang.wu114497ab2024-02-21 14:57:05 +080047 if (blk_no > EDID_MAX_BLOCK)
48 blk_no = EDID_MAX_BLOCK;
Wenjie Qiao389d3ea2023-05-25 16:07:03 +080049
Wenjie Qiao8a73a562023-02-23 18:37:14 +080050 printf("dump EDID rawdata\n");
51 printf(" ");
52 for (i = 0; i < blk_no * EDID_BLK_SIZE; i++)
53 printf("%02x", buf[i]);
54 printf("\n");
55}
56
Wenjie Qiao8a73a562023-02-23 18:37:14 +080057static int do_rx_det(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
58{
59 unsigned char st = 0;
60 struct hdmitx_dev *hdev = get_hdmitx21_device();
61
62 memset(edid_raw_buf, 0, ARRAY_SIZE(edid_raw_buf));
63
lizhi.hu506ddfa2024-07-10 21:35:41 +080064 /*
65 * read edid raw data
66 * current only support read 1 byte edid data
67 */
Wenjie Qiao8a73a562023-02-23 18:37:14 +080068 st = hdev->hwop.read_edid(edid_raw_buf);
69
70 if (st) {
71 if (edid_raw_buf[250] == 0xfb && edid_raw_buf[251] == 0x0c) {
72 printf("RX is FBC\n");
73
lizhi.hu506ddfa2024-07-10 21:35:41 +080074 /* set outputmode ENV */
Wenjie Qiao8a73a562023-02-23 18:37:14 +080075 switch (edid_raw_buf[252] & 0x0f) {
76 case 0x0:
77 run_command("setenv outputmode 1080p50hz", 0);
78 break;
79 case 0x1:
80 run_command("setenv outputmode 2160p50hz420", 0);
81 break;
82 case 0x2:
83 run_command("setenv outputmode 1080p50hz44410bit", 0);
84 break;
85 case 0x3:
86 run_command("setenv outputmode 2160p50hz42010bit", 0);
87 break;
88 case 0x4:
89 run_command("setenv outputmode 2160p50hz42210bit", 0);
90 break;
91 case 0x5:
92 run_command("setenv outputmode 2160p50hz", 0);
93 break;
94 default:
95 run_command("setenv outputmode 1080p50hz", 0);
96 break;
97 }
98
lizhi.hu506ddfa2024-07-10 21:35:41 +080099 /* et RX 3D Info */
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800100 switch ((edid_raw_buf[252] >> 4) & 0x0f) {
101 case 0x00:
102 run_command("setenv rx_3d_info 0", 0);
103 break;
104 case 0x01:
105 run_command("setenv rx_3d_info 1", 0);
106 break;
107 case 0x02:
108 run_command("setenv rx_3d_info 2", 0);
109 break;
110 case 0x03:
111 run_command("setenv rx_3d_info 3", 0);
112 break;
113 case 0x04:
114 run_command("setenv rx_3d_info 4", 0);
115 break;
116 default:
117 break;
118 }
119
120 switch (edid_raw_buf[253]) {
121 case 0x1:
122 /*TODO*/
123 break;
124 case 0x2:
125 /*TODO*/
126 break;
127 default:
128 break;
129 }
130 }
131 } else {
132 printf("edid read failed\n");
133 }
134
135 return st;
136}
137
lizhi.hu506ddfa2024-07-10 21:35:41 +0800138int is_valid_hdmi(const char *input)
139{
140 static const char * const valid_hdmi_modes[] = {
141 "HDMI-A-A", /* venc0 */
142 "HDMI-A-B", /* venc1 */
143 "HDMI-A-C" /* venc2 */
144 };
145
146 int num_modes = ARRAY_SIZE(valid_hdmi_modes);
147 int i;
148
149 for (i = 0; i < num_modes; i++) {
150 if (strcmp(input, valid_hdmi_modes[i]) == 0)
151 return 1;
152 }
153 return 0;
154}
155
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800156static void save_default_720p(void)
157{
158 memcpy(sel_hdmimode, DEFAULT_HDMI_MODE, sizeof(DEFAULT_HDMI_MODE));
lizhi.hu506ddfa2024-07-10 21:35:41 +0800159 if (is_valid_hdmi(env_get("connector0_type"))) {
160 env_set("outputmode", DEFAULT_HDMI_MODE);
161 } else if (is_valid_hdmi(env_get("connector1_type"))) {
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800162 env_set("outputmode2", DEFAULT_HDMI_MODE);
lizhi.hu506ddfa2024-07-10 21:35:41 +0800163 } else if (is_valid_hdmi(env_get("connector2_type"))) {
164 env_set("outputmode3", DEFAULT_HDMI_MODE);
165 } else {
166 pr_info("no config connectorX_type, save default 720p outputmode\n");
167 env_set("outputmode", DEFAULT_HDMI_MODE);
168 }
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800169 env_set("colorattribute", DEFAULT_COLOR_FORMAT);
170}
171
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800172static void hdmitx_mask_rx_info(struct hdmitx_dev *hdev)
173{
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800174 if (!hdev || !hdev->para)
175 return;
176
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800177 if (env_get("colorattribute"))
178 hdmitx21_get_fmtpara(sel_hdmimode, env_get("colorattribute"));
179
lizhi.hu506ddfa2024-07-10 21:35:41 +0800180 /*
181 * when current output color depth is 8bit, mask hdr capability
182 * refer to SWPL-44445 for more detail
183 */
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800184 if (hdev->para->cd == COLORDEPTH_24B)
185 memset(&hdev->RXCap.hdr_info, 0, sizeof(struct hdr_info));
186}
187
lizhi.hu506ddfa2024-07-10 21:35:41 +0800188/*
zongdong.jiaob6fa9962024-08-25 19:51:48 +0800189 * env_get() may return null, so use below to check
190 * if env0 and env1 are same, return 1; else return 0
191 */
192static bool hdmi_cmp_env(const char *env0, const char *env1)
193{
194 if (!env0 && !env1)
195 return 1;
196 if (!env0)
197 return 0;
198 if (!env1)
199 return 0;
200 if (strcmp(env0, env1))
201 return 0;
202 return 1;
203}
204
205#define HDMI_ENV_PARAM_MAX_LEN 32
206static void check_hdmi_env_params(void)
207{
208 static char env_hdmimode[HDMI_ENV_PARAM_MAX_LEN];
209 static char env_outputmode[HDMI_ENV_PARAM_MAX_LEN];
210 static char env_colorattr[HDMI_ENV_PARAM_MAX_LEN];
211 static char env_usercolorattr[HDMI_ENV_PARAM_MAX_LEN];
212 char *tmpstr = NULL;
213
214 /* if 4 hdmi environments are not changing, return */
215 if ((hdmi_cmp_env(env_hdmimode, env_get("hdmimode"))) &&
216 (hdmi_cmp_env(env_outputmode, env_get("outputmode"))) &&
217 (hdmi_cmp_env(env_colorattr, env_get("colorattribute"))) &&
218 (hdmi_cmp_env(env_usercolorattr, env_get("user_colorattribute"))))
219 return;
220
221 /* if changes, print and save those values */
222 tmpstr = env_get("hdmimode");
223 pr_info("hdmimode: %s\n", tmpstr ? tmpstr : "");
224 memset(env_hdmimode, 0, HDMI_ENV_PARAM_MAX_LEN);
225 if (tmpstr)
226 strncpy(env_hdmimode, tmpstr, HDMI_ENV_PARAM_MAX_LEN - 1);
227
228 tmpstr = env_get("outputmode");
229 pr_info("outputmode: %s\n", tmpstr ? tmpstr : "");
230 memset(env_outputmode, 0, HDMI_ENV_PARAM_MAX_LEN);
231 if (tmpstr)
232 strncpy(env_outputmode, tmpstr, HDMI_ENV_PARAM_MAX_LEN - 1);
233
234 tmpstr = env_get("colorattribute");
235 pr_info("colorattribute: %s\n", tmpstr ? tmpstr : "");
236 memset(env_colorattr, 0, HDMI_ENV_PARAM_MAX_LEN);
237 if (tmpstr)
238 strncpy(env_colorattr, tmpstr, HDMI_ENV_PARAM_MAX_LEN - 1);
239
240 tmpstr = env_get("user_colorattribute");
241 pr_info("user_colorattribute: %s\n", tmpstr ? tmpstr : "");
242 memset(env_usercolorattr, 0, HDMI_ENV_PARAM_MAX_LEN);
243 if (tmpstr)
244 strncpy(env_usercolorattr, tmpstr, HDMI_ENV_PARAM_MAX_LEN - 1);
245}
246
247static void save_hdmi_tfr_mode(void)
248{
249 const char *tfr_mode = NULL;
250 const char *mode = NULL;
251 const struct hdmi_timing *tfr_timing = NULL;
252 const struct hdmi_timing *mode_timing = NULL;
253
254 /*
255 * case1: hdmimode not none
256 * if TV changed, hdmimode != outputmode
257 */
258 tfr_mode = env_get("hdmimode");
259 if (tfr_mode) {
260 tfr_timing = hdmitx21_gettiming_from_name(tfr_mode);
261 if (tfr_timing) {
262 mode = env_get("outputmode");
263 mode_timing= hdmitx21_gettiming_from_name(mode);
264 if ((mode_timing->h_active < tfr_timing->h_active) &&
265 (mode_timing->v_freq < tfr_timing->v_freq))
266 env_set("tfr_mode", env_get("outputmode"));
267 else
268 env_set("tfr_mode", env_get("hdmimode"));
269 pr_info("hdmitx: qms: save tfr mode %s from hdmimode\n", tfr_mode);
270 return;
271 }
272 }
273
274 /*
275 * case2: hdmimode as none, or NULL
276 */
277 tfr_mode = env_get("outputmode");
278 if (tfr_mode) {
279 tfr_timing = hdmitx21_gettiming_from_name(tfr_mode);
280 if (tfr_timing) {
281 env_set("tfr_mode", tfr_mode);
282 pr_info("hdmitx: qms: save tfr mode %s from outputmoe\n", tfr_mode);
283 return;
284 }
285 }
286 pr_info("hdmitx: qms: failed to save tfr mode\n");
287}
288
289/*
lizhi.hu506ddfa2024-07-10 21:35:41 +0800290 * If environment qms_en is true, and RX supports QMS, and the
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800291 * output mode is BRR then enable TX QMS
292 */
293static void qms_scene_pre_process(struct hdmitx_dev *hdev)
294{
295 bool env_qms_en = 0;
296 bool rx_qms_cap = 0;
297 enum hdmi_vic qms_brr_vic = HDMI_UNKNOWN;
zongdong.jiaob6fa9962024-08-25 19:51:48 +0800298 const struct hdmi_timing *tfr_timing = NULL;
299 const struct hdmi_timing *brr_timing = NULL;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800300 char *color = NULL;
zongdong.jiao1ac547f2024-03-06 13:43:31 +0800301 const char *i_modes[3] = {
302 "480i", "576i", "1080i",
303 };
304 char *mode;
305 int i;
306
lizhi.hu506ddfa2024-07-10 21:35:41 +0800307 /* default as 0 */
308 hdev->qms_en = 0;
zongdong.jiaob6fa9962024-08-25 19:51:48 +0800309
310 if (hdev->vic == HDMI_UNKNOWN)
311 return;
312
313 rx_qms_cap = hdev->RXCap.qms;
314
315 /* save current hdmimode/outputmode is QMS/TFR mode */
316 if (!rx_qms_cap)
317 return;
318
319 /* check uboot environment */
320 if (env_get("qms_en") && (env_get_ulong("qms_en", 10, 0) == 1))
321 env_qms_en = 1;
322 else
323 return;
324
zongdong.jiao1ac547f2024-03-06 13:43:31 +0800325 /* if current mode is interlaced mode, then skip QMS */
zongdong.jiaob6fa9962024-08-25 19:51:48 +0800326 mode = env_get("outputmode");
zongdong.jiao1ac547f2024-03-06 13:43:31 +0800327 if (!mode)
328 return;
329 for (i = 0; i < 3; i++) {
330 if (strstr(mode, i_modes[i]))
331 return;
332 }
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800333
zongdong.jiaob6fa9962024-08-25 19:51:48 +0800334 check_hdmi_env_params();
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800335
zongdong.jiaob6fa9962024-08-25 19:51:48 +0800336 save_hdmi_tfr_mode();
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800337
zongdong.jiaob6fa9962024-08-25 19:51:48 +0800338 mode = env_get("tfr_mode");
339 if (!mode)
340 return;
341 tfr_timing = hdmitx21_gettiming_from_name(mode);
342 qms_brr_vic = hdmitx_find_brr_vic(tfr_timing->vic);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800343
344 if (env_qms_en && rx_qms_cap && qms_brr_vic != HDMI_UNKNOWN)
345 hdev->qms_en = 1;
zongdong.jiaob6fa9962024-08-25 19:51:48 +0800346 else
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800347 return;
zongdong.jiaob6fa9962024-08-25 19:51:48 +0800348 /* check tfr is less than brr */
349 mode = env_get("outputmode");
350 brr_timing = hdmitx21_gettiming_from_vic(qms_brr_vic);
351 if (brr_timing->v_freq < tfr_timing->v_freq) {
352 hdev->qms_en = 0;
353 color = env_get("colorattribute");
354 hdev->vic = tfr_timing->vic;
355 mode = tfr_timing->sname ? tfr_timing->sname : tfr_timing->name;
356 hdev->para = hdmitx21_get_fmtpara(mode, color);
357 pr_info("hdmitx: qms: tfr %s larger than brr %s\n", env_get("tfr_mode"), mode);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800358 return;
359 }
zongdong.jiaob6fa9962024-08-25 19:51:48 +0800360
361 pr_info("hdmitx: qms: env %d rx %d vic %d brr_vic %d\n",
362 env_qms_en, rx_qms_cap, hdev->vic, qms_brr_vic);
363
364 hdev->brr_vic = qms_brr_vic;
365 /* reconfig the hdmi para */
366 brr_timing = hdmitx21_gettiming_from_vic(hdev->brr_vic);
xiang.wu168a8fa32024-05-27 17:20:43 +0800367 color = env_get("colorattribute");
zongdong.jiao15a19b22024-05-21 15:33:05 +0800368 /* save brr_vic to vic without the environment */
369 hdev->vic = hdev->brr_vic;
zongdong.jiaob6fa9962024-08-25 19:51:48 +0800370 mode = brr_timing->sname ? brr_timing->sname : brr_timing->name;
371 hdev->para = hdmitx21_get_fmtpara(mode, color);
372 check_hdmi_env_params();
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800373}
374
375static void qms_scene_post_process(struct hdmitx_dev *hdev)
376{
zongdong.jiaob6fa9962024-08-25 19:51:48 +0800377 if (!hdev->qms_en)
378 return;
zongdong.jiao15a19b22024-05-21 15:33:05 +0800379
lizhi.hu506ddfa2024-07-10 21:35:41 +0800380 /* Init QMS parameter */
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800381 vrr_init_qms_para(hdev);
zongdong.jiaob6fa9962024-08-25 19:51:48 +0800382 env_set("tfr_mode", NULL);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800383}
384
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800385static int do_output(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
386{
387 const struct hdmi_timing *timing = NULL;
388 struct hdmitx_dev *hdev = get_hdmitx21_device();
389
xiang.wu1a6d6f1d2023-08-04 14:13:00 +0800390#ifdef CONFIG_PXP_EMULATOR
391 hdmitx21_pxp_init(1);
392#endif
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800393 if (argc < 1)
394 return cmd_usage(cmdtp);
395
396 if (strcmp(argv[1], "list") == 0) {
397 hdev->hwop.list_support_modes();
398 } else if (strcmp(argv[1], "bist") == 0) {
399 unsigned int mode = 0;
400
401 if (strcmp(argv[2], "off") == 0)
402 mode = 0;
403 else if (strcmp(argv[2], "line") == 0)
404 mode = 2;
405 else if (strcmp(argv[2], "dot") == 0)
406 mode = 3;
407 else if (strcmp(argv[2], "x") == 0)
408 mode = 'x';
409 else if (strcmp(argv[2], "X") == 0)
410 mode = 'X';
411 else
412 mode = simple_strtoul(argv[2], NULL, 10);
413 hdev->hwop.test_bist(mode);
414 } else if (strcmp(argv[1], "prbs") == 0) {
415 hdev->para->cs = HDMI_COLORSPACE_RGB;
416 hdev->para->cd = COLORDEPTH_24B;
417 hdev->vic = HDMI_16_1920x1080p60_16x9;
418 hdmitx21_set(hdev);
419 hdev->hwop.test_prbs();
420 } else if (strncmp(argv[1], "div40", 5) == 0) {
421 bool div40 = 0;
422
423 if (argv[1][5] == '1')
424 div40 = 1;
425 hdev->hwop.set_div40(div40);
426 } else { /* "output" */
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800427 if (!hdev->pxp_mode) {
xiang.wu114497ab2024-02-21 14:57:05 +0800428 if (!hdmitx_edid_check_data_valid(0, hdev->rawedid)) {
lizhi.hu506ddfa2024-07-10 21:35:41 +0800429 /*
430 * in SWPL-34712: if EDID parsing error in kernel,
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800431 * only forcely output default mode(480p,RGB,8bit)
432 * in sysctl, not save the default mode to env.
433 * if uboot follow this rule, will cause issue OTT-19333:
434 * uboot read edid error and then output default mode,
435 * without save it mode env. if then kernel edid normal,
436 * sysctrl/kernel get mode from env, the actual output
437 * mode differs with outputmode env,it will
438 * cause display abnormal(such as stretch). so don't
439 * follow this rule in uboot, that's to say the actual
440 * output mode needs to stays with the outputmode env.
441 */
442 printf("edid parsing ng, forcely output 720p, rgb,8bit\n");
443 save_default_720p();
444 hdev->vic = HDMI_4_1280x720p60_16x9;
445 hdev->para =
446 hdmitx21_get_fmtpara("720p60hz", "rgb,8bit");
447 hdev->para->cs = HDMI_COLORSPACE_RGB;
448 hdev->para->cd = COLORDEPTH_24B;
449 hdmitx21_set(hdev);
450 return CMD_RET_SUCCESS;
451 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800452 }
453 if (!env_get("colorattribute"))
454 env_set("colorattribute", "444,8bit");
zongdong.jiaob6fa9962024-08-25 19:51:48 +0800455 /* if QMS is enabled, no need to use argv[1] */
456 if (!hdev->qms_en) {
457 hdev->para = hdmitx21_get_fmtpara(argv[1], env_get("colorattribute"));
458 hdev->vic = hdev->para->timing.vic;
459 }
xiang.wu114497ab2024-02-21 14:57:05 +0800460 if (hdev->vic == HDMI_0_UNKNOWN) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800461 /* Not find VIC */
462 printf("Not find '%s' mapped VIC\n", argv[1]);
463 return CMD_RET_FAILURE;
464 }
465 if (strstr(argv[1], "hz420"))
466 hdev->para->cs = HDMI_COLORSPACE_YUV420;
467 /* S5 support over 6G, T7 not support */
468 switch (hdev->vic) {
469 case HDMI_96_3840x2160p50_16x9:
470 case HDMI_97_3840x2160p60_16x9:
471 case HDMI_101_4096x2160p50_256x135:
472 case HDMI_102_4096x2160p60_256x135:
473 case HDMI_106_3840x2160p50_64x27:
474 case HDMI_107_3840x2160p60_64x27:
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800475 if (hdev->chip_type != MESON_CPU_ID_S5) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800476 if (hdev->para->cs == HDMI_COLORSPACE_RGB ||
477 hdev->para->cs == HDMI_COLORSPACE_YUV444) {
478 if (hdev->para->cd != COLORDEPTH_24B) {
479 printf("vic %d cs %d has no cd %d\n",
480 hdev->vic,
481 hdev->para->cs,
482 hdev->para->cd);
483 hdev->para->cd = COLORDEPTH_24B;
484 printf("set cd as %d\n", COLORDEPTH_24B);
485 }
486 }
487 }
488 break;
489 default:
lizhi.hu506ddfa2024-07-10 21:35:41 +0800490 /*
491 * In Spec2.1 Table 7-34, v_active greater than or equal to 2160 and refresh
zhou.hanaccf2ad2024-06-29 11:36:03 +0800492 * rate greater than 30 will support y420
493 * Only the S5 will run this case, because 4k 50/60hz has already been
494 * filtered and only S5 support over 6G (4k 100/120hz)
495 */
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800496 timing = hdmitx21_gettiming_from_vic(hdev->vic);
497 if (!timing)
498 break;
zhou.hanaccf2ad2024-06-29 11:36:03 +0800499 if (timing->v_active >= 2160 && timing->v_freq > 30000)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800500 break;
501 if (timing->v_active >= 4320)
502 break;
503 if (hdev->para->cs == HDMI_COLORSPACE_YUV420) {
504 printf("vic %d has no cs %d\n", hdev->vic,
505 hdev->para->cs);
506 hdev->para->cs = HDMI_COLORSPACE_YUV444;
507 printf("set cs as %d\n", HDMI_COLORSPACE_YUV444);
508 }
509 break;
510 }
511 printf("set hdmitx VIC = %d CS = %d CD = %d\n",
512 hdev->vic, hdev->para->cs, hdev->para->cd);
lizhi.hu506ddfa2024-07-10 21:35:41 +0800513 /*
514 * currently, hdmi mode is always set, if
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800515 * mode set abort/exit, need to add return
516 * result of mode setting, so that vout
517 * driver will pass it to kernel, and do
518 * mode setting again when vout init in kernel
519 */
zongdong.jiaob6fa9962024-08-25 19:51:48 +0800520 qms_scene_pre_process(hdev);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800521 hdmitx21_set(hdev);
xiang.wu15613f462024-09-04 17:42:04 +0800522 /* for special LG TV, need send ake_init first */
523 if (hdmitx_find_send_ake_init(hdev->rawedid))
524 hdmitx21_send_ake_init();
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800525 qms_scene_post_process(hdev);
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800526 if (hdev->para->frl_rate && !hdev->flt_train_st) {
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800527 /* FLT training failed, need go to tmds mode */
528 printf("hdmitx frl training failed, set tmds mode\n");
xiang.wu1dba66a02024-05-28 19:53:01 +0800529 hdmitx_module_disable();
530 hdev->frl_train_fail_flag = true;
531 run_command("run init_display", 0);
Wenjie Qiao389d3ea2023-05-25 16:07:03 +0800532 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800533 }
534 return CMD_RET_SUCCESS;
535}
536
537static int do_clkmsr(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
538{
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800539 struct hdmitx_dev *hdev = get_hdmitx21_device();
540
541 if (hdev->chip_type == MESON_CPU_ID_S5) {
542 clk_msr(4);
543 clk_msr(8);
544 clk_msr(16);
545 clk_msr(27);
546 clk_msr(63);
547 clk_msr(64);
548 clk_msr(66);
549 clk_msr(68);
550 clk_msr(69);
551 clk_msr(70);
552 clk_msr(71);
553 clk_msr(72);
554 clk_msr(73);
555 clk_msr(74);
556 clk_msr(75);
557 clk_msr(76);
558 clk_msr(79);
559 clk_msr(82);
560 clk_msr(89);
561 clk_msr(90);
562 clk_msr(91);
563 clk_msr(92);
564 clk_msr(93);
565 clk_msr(94);
566 clk_msr(95);
567 return CMD_RET_SUCCESS;
568 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800569 clk_msr(51);
570 clk_msr(59);
571 clk_msr(61);
572 clk_msr(76);
573 clk_msr(77);
574 clk_msr(78);
575 clk_msr(80);
576 clk_msr(81);
577 clk_msr(82);
578 clk_msr(83);
579 clk_msr(219);
580 clk_msr(220);
581 clk_msr(221);
582 clk_msr(222);
583 return CMD_RET_SUCCESS;
584}
585
586static int do_blank(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
587{
588 struct hdmitx_dev *hdev = get_hdmitx21_device();
589
590 if (argc < 1)
591 return cmd_usage(cmdtp);
592
593 if (strcmp(argv[1], "1") == 0)
594 hdev->hwop.output_blank(1);
595 if (strcmp(argv[1], "0") == 0)
596 hdev->hwop.output_blank(0);
597
598 return CMD_RET_SUCCESS;
599}
600
601static int do_off(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
602{
603 struct hdmitx_dev *hdev = get_hdmitx21_device();
604
xiang.wu114497ab2024-02-21 14:57:05 +0800605 hdev->vic = HDMI_0_UNKNOWN;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +0800606 if (hdev->chip_type == MESON_CPU_ID_S5)
607 hdmitx_module_disable();
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800608 hdev->hwop.turn_off();
609 printf("turn off hdmitx\n");
610 return 1;
611}
612
613static int do_dump(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
614{
615 struct hdmitx_dev *hdev = get_hdmitx21_device();
616
617 hdev->hwop.dump_regs();
618 return 1;
619}
620
621static int do_reg(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
622{
623 unsigned long addr = 0;
624 unsigned int data = 0;
625
626 if (argc < 1)
627 return cmd_usage(cmdtp);
628
629 if (strncmp(argv[1], "rh", 2) == 0) {
630 addr = strtoul(argv[1] + 2, NULL, 16);
631 data = hdmitx21_rd_reg((unsigned int)addr);
632 printf("rd[0x%lx] 0x%x\n", addr, data);
633 }
634
635 if (strncmp(argv[1], "wh", 2) == 0) {
636 addr = strtoul(argv[1] + 2, NULL, 16);
637 data = strtoul(argv[2], NULL, 16);
638 hdmitx21_wr_reg(addr, data);
639 printf("wr[0x%lx] 0x%x\n", addr, data);
640 }
641
642 return 1;
643}
644
xiang.wu1a6d6f1d2023-08-04 14:13:00 +0800645static int do_pbist(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
646{
647 struct hdmitx_dev *hdev = get_hdmitx21_device();
648
649 if (strcmp(argv[1], "1") == 0)
650 hdmitx21_pbist_config(hdev, hdev->vic, 1);
651 if (strcmp(argv[1], "0") == 0)
652 hdmitx21_pbist_config(hdev, hdev->vic, 0);
653 return 1;
654}
655
zhou.han89696e82024-12-26 11:38:28 +0800656static int do_clk_path_config(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
xiang.wu1492f3642024-01-08 14:06:40 +0800657{
658 struct hdmitx_dev *hdev = get_hdmitx21_device();
659
660 if (strcmp(argv[1], "1") == 0) {
zhou.han89696e82024-12-26 11:38:28 +0800661 hdev->clk_analog_path = 1;
662 pr_info("clk_analog_path = %d\n", hdev->clk_analog_path);
xiang.wu1492f3642024-01-08 14:06:40 +0800663 } if (strcmp(argv[1], "0") == 0) {
zhou.han89696e82024-12-26 11:38:28 +0800664 hdev->clk_analog_path = 0;
665 pr_info("clk_analog_path = %d\n", hdev->clk_analog_path);
xiang.wu1492f3642024-01-08 14:06:40 +0800666 }
667 return 1;
668}
669
xiang.wu114497ab2024-02-21 14:57:05 +0800670static int get_rterm(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
671{
672 struct arm_smccc_res res;
673 u8 rterm_efuse;
674
675 arm_smccc_smc(HDCPTX_IOOPR, HDMITX_GET_RTERM, 0, 0, 0, 0, 0, 0, &res);
676 rterm_efuse = (unsigned int)((res.a0) & 0xffffffff);
677 pr_info("rterm_efuse = %d\n", rterm_efuse);
678 return 1;
679}
680
xiang.wu1a6d6f1d2023-08-04 14:13:00 +0800681static int do_debug(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
682{
683 unsigned int enable_all = 0;
684 int pkt_op = 0;
685 unsigned int mov_val = 0;
686 unsigned char pb[28] = {0x46, 0xD0, 0x00, 0x00, 0x00, 0x00, 0x46, 0xD0,
687 0x00, 0x10, 0x21, 0xaa, 0x9b, 0x96, 0x19, 0xfc, 0x19, 0x75, 0xd5, 0x78,
688 0x10, 0x21, 0xaa, 0x9b, 0x96, 0x19, 0xfc, 0x19};
689 unsigned char hb[3] = {0x01, 0x02, 0x03};
690
691 if (argc < 1)
692 return cmd_usage(cmdtp);
693
694 if (strncmp(argv[1], "pkt", 3) == 0) {
695 enable_all = strtoul(argv[1] + 3, NULL, 16);
696 pkt_op = strtoul(argv[2], NULL, 16);
697 mov_val = strtoul(argv[3], NULL, 10);
698 pkt_send_position_change(enable_all, pkt_op, mov_val);
699 } else if (strncmp(argv[1], "w_dhdr", 6) == 0 ) {
700 hdmitx21_write_dhdr_sram();
701 } else if (strncmp(argv[1], "r_dhdr", 6) == 0 ) {
702 hdmitx21_read_dhdr_sram();
703 } else if (strncmp(argv[1], "t_avi", 4) == 0 ) {
704 printf("test send avi pkt\n");
705 hdmi_avi_infoframe_rawset(hb, pb);
706 } else if (strncmp(argv[1], "t_audio", 7) == 0 ) {
707 printf("test send audio pkt\n");
708 hdmi_audio_infoframe_rawset(hb, pb);
709 } else if (strncmp(argv[1], "t_sbtm", 6) == 0 ) {
710 printf("test send SBTM pkt\n");
711 hdmitx21_send_sbtm_pkt();
712 }
713
714 return 1;
715}
716
lizhi.hu506ddfa2024-07-10 21:35:41 +0800717/*
718 * step1, only select VIC which is supported in EDID
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800719 * step2, check if VIC is supported by SOC hdmitx
720 * step3, build format with basic mode/attr and check
721 * if it's supported by EDID/hdmitx_cap
722 */
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800723static void disp_cap_show(struct hdmitx_dev *hdev)
724{
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800725 if (!hdev)
726 return;
727
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800728 struct rx_cap *prxcap = &hdev->RXCap;
729 const struct hdmi_timing *timing = NULL;
730 enum hdmi_vic vic;
731 int i = 0;
732 int vic_len = prxcap->VIC_count + VESA_MAX_TIMING;
733 int *edid_vics = vmalloc(vic_len * sizeof(int));
734 enum hdmi_vic prefer_vic = HDMI_0_UNKNOWN;
735
736 memset(edid_vics, 0, vic_len * sizeof(int));
737
lizhi.hu506ddfa2024-07-10 21:35:41 +0800738 /*
739 * step1: only select VIC which is supported in EDID
740 * copy edid vic list
741 */
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800742 if (prxcap->VIC_count > 0)
743 memcpy(edid_vics, prxcap->VIC, sizeof(int) * prxcap->VIC_count);
744 for (i = 0; i < VESA_MAX_TIMING && prxcap->vesa_timing[i]; i++)
745 edid_vics[prxcap->VIC_count + i] = prxcap->vesa_timing[i];
746
747 for (i = 0; i < vic_len; i++) {
748 vic = edid_vics[i];
749 if (vic == HDMI_0_UNKNOWN)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800750 continue;
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800751
752 prefer_vic = hdmitx_get_prefer_vic(hdev, vic);
753 /* if mode_best_vic is support by RX, try 16x9 first */
zhou.hana8e91612024-04-28 14:56:45 +0000754 if (prefer_vic != vic) {
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800755 pr_info("%s: check prefer vic:%d exist, ignore [%d].\n",
756 __func__, prefer_vic, vic);
zhou.hana8e91612024-04-28 14:56:45 +0000757 continue;
758 }
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800759
760 timing = hdmitx_mode_vic_to_hdmi_timing(vic);
761 if (!timing) {
lizhi.hu506ddfa2024-07-10 21:35:41 +0800762 /* HDMITX_ERROR("%s: unsupport vic [%d]\n", __func__, vic); */
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800763 continue;
764 }
765
766 /* step2, check if VIC is supported by SOC hdmitx */
767 if (hdmitx_common_validate_vic(&hdev->tx_common, vic) != 0) {
lizhi.hu506ddfa2024-07-10 21:35:41 +0800768 /* HDMITX_ERROR("%s: vic[%d] over range.\n", __func__, vic); */
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800769 continue;
770 }
771
lizhi.hu506ddfa2024-07-10 21:35:41 +0800772 /*
773 * step3, build format with basic mode/attr and check
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800774 * if it's supported by EDID/hdmitx_cap
775 */
776 if (hdmitx_common_check_valid_para_of_vic(&hdev->tx_common, vic) != 0) {
lizhi.hu506ddfa2024-07-10 21:35:41 +0800777 /* HDMITX_ERROR("%s: vic[%d] check fmt attr failed.\n", __func__, vic); */
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800778 continue;
779 }
780
781 printf(" %s\n", timing->sname ? timing->sname : timing->name);
782
783 if (vic == prxcap->native_vic)
784 printf("*\n");
785 else
786 printf("\n");
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800787 }
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800788
xiang.wu114497ab2024-02-21 14:57:05 +0800789 printf("420_cap\n");
790 for (i = 0; i < Y420_VIC_MAX_NUM; i++) {
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800791 vic = prxcap->y420_vic[i];
xiang.wu114497ab2024-02-21 14:57:05 +0800792 printf("420vic:%d\n", vic);
793 }
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800794 vfree(edid_vics);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800795}
796
797static void vesa_cap_show(struct hdmitx_dev *hdev)
798{
799}
800
801static void dc_cap_show(struct hdmitx_dev *hdev)
802{
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800803 struct rx_cap *prxcap = &hdev->RXCap;
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800804 const struct dv_info *dv = &prxcap->dv_info;
805 const struct dv_info *dv2 = &prxcap->dv_info2;
806 int i;
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800807
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800808 /* DVI case, only rgb,8bit */
809 if (prxcap->ieeeoui != HDMI_IEEE_OUI) {
810 printf("rgb,8bit\n");
811 return;
812 }
813
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800814 if (prxcap->dc_36bit_420)
815 printf("420,12bit\n");
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800816 if (prxcap->dc_30bit_420)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800817 printf("420,10bit\n");
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800818
819 for (i = 0; i < Y420_VIC_MAX_NUM; i++) {
820 if (prxcap->y420_vic[i]) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800821 printf("420,8bit\n");
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800822 break;
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800823 }
824 }
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800825
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800826 if (prxcap->native_Mode & (1 << 5)) {
827 if (prxcap->dc_y444) {
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800828 if (prxcap->dc_36bit || dv->sup_10b_12b_444 == 0x2 ||
829 dv2->sup_10b_12b_444 == 0x2)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800830 printf("444,12bit\n");
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800831 if (prxcap->dc_30bit || dv->sup_10b_12b_444 == 0x1 ||
832 dv2->sup_10b_12b_444 == 0x1) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800833 printf("444,10bit\n");
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800834 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800835 }
836 printf("444,8bit\n");
837 }
838 /* y422, not check dc */
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800839 if (prxcap->native_Mode & (1 << 4))
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800840 printf("422,12bit\n");
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800841
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800842 if (prxcap->dc_36bit || dv->sup_10b_12b_444 == 0x2 ||
843 dv2->sup_10b_12b_444 == 0x2)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800844 printf("rgb,12bit\n");
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +0800845 if (prxcap->dc_30bit || dv->sup_10b_12b_444 == 0x1 ||
846 dv2->sup_10b_12b_444 == 0x1)
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800847 printf("rgb,10bit\n");
848 printf("rgb,8bit\n");
849}
850
851static void aud_cap_show(struct hdmitx_dev *hdev)
852{
ruofei.zhao325a6542024-12-18 11:25:45 +0800853 struct rx_cap *prxcap = &hdev->RXCap;
854 int i, j;
855 struct dolby_vsadb_cap *cap = &prxcap->dolby_vsadb_cap;
856 static const char * const aud_ct[] = {
857 "ReferToStreamHeader", "PCM", "AC-3", "MPEG1", "MP3",
858 "MPEG2", "AAC", "DTS", "ATRAC", "OneBitAudio",
859 "Dolby_Digital+", "DTS-HD", "MAT", "DST", "WMA_Pro",
860 "Reserved", NULL};
861 static const char * const aud_sampling_frequency[] = {
862 "ReferToStreamHeader", "32", "44.1", "48", "88.2", "96",
863 "176.4", "192", NULL};
864 const char * const aud_sample_size[] = {"ReferToStreamHeader",
865 "16", "20", "24", NULL};
866
867 printf("\naud_cap\n");
868 printf("CodingType MaxChannels SamplingFreq SampleSize\n");
869 for (i = 0; i < prxcap->AUD_count; i++) {
870 if (prxcap->RxAudioCap[i].audio_format_code == CT_CXT) {
871 if ((prxcap->RxAudioCap[i].cc3 >> 3) == 0xb) {
872 printf("MPEG-H, 8ch, ");
873 for (j = 0; j < 7; j++) {
874 if (prxcap->RxAudioCap[i].freq_cc & (1 << j))
875 printf("%s/", aud_sampling_frequency[j + 1]);
876 }
877 printf(" kHz\n");
878 }
879 continue;
880 }
881 printf("%s", aud_ct[prxcap->RxAudioCap[i].audio_format_code]);
882 if (prxcap->RxAudioCap[i].audio_format_code == CT_DD_P &&
883 (prxcap->RxAudioCap[i].cc3 & 1))
884 printf("/ATMOS");
885 if (prxcap->RxAudioCap[i].audio_format_code != CT_CXT)
886 printf(", %d ch, ", prxcap->RxAudioCap[i].channel_num_max + 1);
887 for (j = 0; j < 7; j++) {
888 if (prxcap->RxAudioCap[i].freq_cc & (1 << j))
889 printf("%s/", aud_sampling_frequency[j + 1]);
890 }
891 printf(" kHz, ");
892 switch (prxcap->RxAudioCap[i].audio_format_code) {
893 case CT_PCM:
894 for (j = 0; j < 3; j++) {
895 if (prxcap->RxAudioCap[i].cc3 & (1 << j))
896 printf("%s/", aud_sample_size[j + 1]);
897 }
898 printf(" bit\n");
899 break;
900 case CT_AC_3:
901 case CT_MPEG1:
902 case CT_MP3:
903 case CT_MPEG2:
904 case CT_AAC:
905 case CT_DTS:
906 case CT_ATRAC:
907 case CT_ONE_BIT_AUDIO:
908 printf("MaxBitRate %dkHz\n", prxcap->RxAudioCap[i].cc3 * 8);
909 break;
910 case CT_DD_P:
911 case CT_DTS_HD:
912 case CT_MAT:
913 case CT_DST:
914 printf("DepValue 0x%x\n", prxcap->RxAudioCap[i].cc3);
915 break;
916 case CT_WMA:
917 default:
918 break;
919 }
920 }
921
922 if (cap->ieeeoui == DOVI_IEEEOUI) {
923 /*
924 * Dolby Vendor Specific:
925 * headphone_playback_only:0,
926 * center_speaker:1,
927 * surround_speaker:1,
928 * height_speaker:1,
929 * Ver:1.0,
930 * MAT_PCM_48kHz_only:1,
931 * e61146d0007001,
932 */
933 printf("Dolby Vendor Specific:\n");
934 if (cap->dolby_vsadb_ver == 0)
935 printf(" Ver:1.0,\n");
936 else
937 printf(" Ver:Reversed,\n");
938 printf(" center_speaker:%d,\n", cap->spk_center);
939 printf(" surround_speaker:%d,\n", cap->spk_surround);
940 printf(" height_speaker:%d,\n", cap->spk_height);
941 printf(" headphone_playback_only:%d,\n", cap->headphone_only);
942 printf(" MAT_PCM_48kHz_only:%d,\n", cap->mat_48k_pcm_only);
943
944 printf(" ");
945 for (i = 0; i < 7; i++)
946 printf("%02x", cap->rawdata[i]);
947 printf(",\n");
948 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800949}
950
951static void hdr_cap_show(struct hdmitx_dev *hdev)
952{
953 int hdr10plugsupported = 0;
954 struct hdr_info *hdr = &hdev->RXCap.hdr_info;
xiang.wu114497ab2024-02-21 14:57:05 +0800955 const struct hdr10_plus_info *hdr10p = &hdev->RXCap.hdr_info.hdr10plus_info;
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800956
957 printf("\nhdr_cap\n");
958 if (hdr10p->ieeeoui == HDR10_PLUS_IEEE_OUI &&
959 hdr10p->application_version != 0xFF)
960 hdr10plugsupported = 1;
961 printf("HDR10Plus Supported: %d\n", hdr10plugsupported);
962 printf("HDR Static Metadata:\n");
963 printf(" Supported EOTF:\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800964 printf(" Traditional SDR: %d\n", !!(hdr->hdr_support & HDR_SUP_EOTF_SDR));
965 printf(" Traditional HDR: %d\n", !!(hdr->hdr_support & HDR_SUP_EOTF_HDR));
966 printf(" SMPTE ST 2084: %d\n", !!(hdr->hdr_support & HDR_SUP_EOTF_SMPTE_ST_2084));
967 printf(" Hybrid Log-Gamma: %d\n", !!(hdr->hdr_support & HDR_SUP_EOTF_HLG));
968 printf(" Supported SMD type1: %d\n", hdr->static_metadata_type1);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800969 printf(" Luminance Data\n");
xiang.wu114497ab2024-02-21 14:57:05 +0800970 printf(" Max: %d\n", hdr->lumi_max);
971 printf(" Avg: %d\n", hdr->lumi_avg);
972 printf(" Min: %d\n\n", hdr->lumi_min);
Wenjie Qiao8a73a562023-02-23 18:37:14 +0800973 printf("HDR Dynamic Metadata:");
974}
975
976static void _dv_cap_show(const struct dv_info *dv)
977{
978 int i;
979
980 if (dv->ieeeoui != DV_IEEE_OUI || dv->block_flag != CORRECT) {
981 printf("The Rx don't support DolbyVision\n");
982 return;
983 }
984 printf("DolbyVision RX support list:\n");
985
986 if (dv->ver == 0) {
987 printf("VSVDB Version: V%d\n", dv->ver);
988 printf("2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
989 printf("Support mode:\n");
990 printf(" DV_RGB_444_8BIT\n");
991 if (dv->sup_yuv422_12bit)
992 printf(" DV_YCbCr_422_12BIT\n");
993 }
994 if (dv->ver == 1) {
995 printf("VSVDB Version: V%d(%d-byte)\n", dv->ver, dv->length + 1);
996 if (dv->length == 0xB) {
997 printf("2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
998 printf("Support mode:\n");
999 printf(" DV_RGB_444_8BIT\n");
1000 if (dv->sup_yuv422_12bit)
1001 printf(" DV_YCbCr_422_12BIT\n");
1002 if (dv->low_latency == 0x01)
1003 printf(" LL_YCbCr_422_12BIT\n");
1004 }
1005
1006 if (dv->length == 0xE) {
1007 printf("2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
1008 printf("Support mode:\n");
1009 printf(" DV_RGB_444_8BIT\n");
1010 if (dv->sup_yuv422_12bit)
1011 printf(" DV_YCbCr_422_12BIT\n");
1012 }
1013 }
1014 if (dv->ver == 2) {
1015 printf("VSVDB Version: V%d\n", dv->ver);
1016 printf("2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
1017 printf("Support mode:\n");
1018 if (dv->Interface != 0x00 && dv->Interface != 0x01) {
1019 printf(" DV_RGB_444_8BIT\n");
1020 if (dv->sup_yuv422_12bit)
1021 printf(" DV_YCbCr_422_12BIT\n");
1022 }
1023 printf(" LL_YCbCr_422_12BIT\n");
1024 if (dv->Interface == 0x01 || dv->Interface == 0x03) {
1025 if (dv->sup_10b_12b_444 == 0x1)
1026 printf(" LL_RGB_444_10BIT\n");
1027 if (dv->sup_10b_12b_444 == 0x2)
1028 printf(" LL_RGB_444_12BIT\n");
1029 }
1030 }
1031 printf("IEEEOUI: 0x%06x\n", dv->ieeeoui);
1032 printf("VSVDB: ");
1033 for (i = 0; i < (dv->length + 1); i++)
1034 printf("%02x", dv->rawdata[i]);
1035 printf("\n");
1036}
1037
1038static void dv_cap_show(struct hdmitx_dev *hdev)
1039{
1040 const struct dv_info *dv = &hdev->RXCap.dv_info;
1041
1042 printf("dv_cap\n");
1043 if (dv->ieeeoui != DV_IEEE_OUI) {
1044 printf("The Rx don't support DolbyVision\n");
1045 return;
1046 }
1047 _dv_cap_show(dv);
1048}
1049
1050static void edid_cap_show(struct hdmitx_dev *hdev)
1051{
1052 int i;
1053 struct rx_cap *prxcap = &hdev->RXCap;
1054
xiang.wu114497ab2024-02-21 14:57:05 +08001055 printf("Rx EDID Parse:\n");
1056 printf("Rx Manufacturer Name: %s\n", prxcap->IDManufacturerName);
1057 printf("Rx Product Code: %02x%02x\n",
1058 prxcap->IDProductCode[0], prxcap->IDProductCode[1]);
1059 printf("Rx Serial Number: %02x%02x%02x%02x\n",
1060 prxcap->IDSerialNumber[0],
1061 prxcap->IDSerialNumber[1],
1062 prxcap->IDSerialNumber[2],
1063 prxcap->IDSerialNumber[3]);
1064 printf("Rx Product Name: %s\n", prxcap->ReceiverProductName);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001065
xiang.wu114497ab2024-02-21 14:57:05 +08001066 printf("Manufacture Week: %d\n", prxcap->manufacture_week);
1067 printf("Manufacture Year: %d\n", prxcap->manufacture_year + 1990);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001068
xiang.wu114497ab2024-02-21 14:57:05 +08001069 printf("Physical size(mm): %d x %d\n",
1070 prxcap->physical_width, prxcap->physical_height);
1071
1072 printf("EDID Version: %d.%d\n",
1073 prxcap->edid_version, prxcap->edid_revision);
1074
lizhi.hu506ddfa2024-07-10 21:35:41 +08001075/*
1076 * printf(
xiang.wu114497ab2024-02-21 14:57:05 +08001077 * "EDID block number: 0x%x\n", tx_comm->EDID_buf[0x7e]);
xiang.wu114497ab2024-02-21 14:57:05 +08001078 */
1079
ruofei.zhao325a6542024-12-18 11:25:45 +08001080 printf("Source Physical Address[a.b.c.d]: %x.%x.%x.%x\n",
1081 prxcap->vsdb_phy_addr.a, prxcap->vsdb_phy_addr.b,
1082 prxcap->vsdb_phy_addr.c, prxcap->vsdb_phy_addr.d);
1083
lizhi.hu506ddfa2024-07-10 21:35:41 +08001084 /* TODO native_vic2 */
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001085 printf("native Mode %x, VIC (native %d):\n",
xiang.wu114497ab2024-02-21 14:57:05 +08001086 prxcap->native_Mode, prxcap->native_vic);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001087
1088 printf("ColorDeepSupport %x\n", prxcap->ColorDeepSupport);
1089
xiang.wu114497ab2024-02-21 14:57:05 +08001090 for (i = 0; i < prxcap->VIC_count ; i++) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001091 printf("%d ", prxcap->VIC[i]);
xiang.wu114497ab2024-02-21 14:57:05 +08001092 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001093 printf("\n");
xiang.wu114497ab2024-02-21 14:57:05 +08001094 printf("Audio {format, channel, freq, cce}\n");
1095 for (i = 0; i < prxcap->AUD_count; i++) {
1096 printf("{%d, %d, %x, %x}\n",
1097 prxcap->RxAudioCap[i].audio_format_code,
1098 prxcap->RxAudioCap[i].channel_num_max,
1099 prxcap->RxAudioCap[i].freq_cc,
1100 prxcap->RxAudioCap[i].cc3);
1101 }
1102 printf("Speaker Allocation: %x\n", prxcap->RxSpeakerAllocation);
1103 printf("Vendor: 0x%x ( %s device)\n", prxcap->ieeeoui, (prxcap->ieeeoui) ? "HDMI" : "DVI");
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001104
1105 printf("MaxTMDSClock1 %d MHz\n", prxcap->Max_TMDS_Clock1 * 5);
1106
xiang.wu114497ab2024-02-21 14:57:05 +08001107 if (prxcap->hf_ieeeoui) {
1108 printf("Vendor2: 0x%x\n",
1109 prxcap->hf_ieeeoui);
1110 printf("MaxTMDSClock2 %d MHz\n",
1111 prxcap->Max_TMDS_Clock2 * 5);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001112 }
1113
xiang.wu114497ab2024-02-21 14:57:05 +08001114 printf("MaxFRLRate: %d\n", prxcap->max_frl_rate);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001115
xiang.wu114497ab2024-02-21 14:57:05 +08001116 if (prxcap->allm)
1117 printf("ALLM: %x\n", prxcap->allm);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001118
xiang.wu114497ab2024-02-21 14:57:05 +08001119 if (prxcap->cnc3)
1120 printf("Game/CNC3: %x\n", prxcap->cnc3);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001121
xiang.wu114497ab2024-02-21 14:57:05 +08001122 printf("vLatency: ");
1123 if (prxcap->vLatency == LATENCY_INVALID_UNKNOWN)
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001124 printf(" Invalid/Unknown\n");
xiang.wu114497ab2024-02-21 14:57:05 +08001125 else if (prxcap->vLatency == LATENCY_NOT_SUPPORT)
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001126 printf(" UnSupported\n");
1127 else
xiang.wu114497ab2024-02-21 14:57:05 +08001128 printf(" %d\n", prxcap->vLatency);
1129
1130 printf("aLatency: ");
1131 if (prxcap->aLatency == LATENCY_INVALID_UNKNOWN)
1132 printf(" Invalid/Unknown\n");
1133 else if (prxcap->aLatency == LATENCY_NOT_SUPPORT)
1134 printf(" UnSupported\n");
1135 else
1136 printf(" %d\n", prxcap->aLatency);
1137
1138 printf("i_vLatency: ");
1139 if (prxcap->i_vLatency == LATENCY_INVALID_UNKNOWN)
1140 printf(" Invalid/Unknown\n");
1141 else if (prxcap->i_vLatency == LATENCY_NOT_SUPPORT)
1142 printf(" UnSupported\n");
1143 else
1144 printf(" %d\n", prxcap->i_vLatency);
1145
1146 printf("i_aLatency: ");
1147 if (prxcap->i_aLatency == LATENCY_INVALID_UNKNOWN)
1148 printf(" Invalid/Unknown\n");
1149 else if (prxcap->i_aLatency == LATENCY_NOT_SUPPORT)
1150 printf(" UnSupported\n");
1151 else
1152 printf(" %d\n", prxcap->i_aLatency);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001153
1154 if (prxcap->colorimetry_data)
1155 printf("ColorMetry: 0x%x\n", prxcap->colorimetry_data);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001156
xiang.wu114497ab2024-02-21 14:57:05 +08001157 printf("SCDC: %x\n", prxcap->scdc_present);
1158
1159 printf("RR_Cap: %x\n",
1160 prxcap->scdc_rr_capable);
1161 printf("LTE_340M_Scramble: %x\n",
1162 prxcap->lte_340mcsc_scramble);
1163 /* dsc capability */
1164 printf("dsc_10bpc: %d\n",
1165 prxcap->dsc_10bpc);
1166 printf("dsc_12bpc: %d\n",
1167 prxcap->dsc_12bpc);
1168 printf("dsc_16bpc: %d\n",
1169 prxcap->dsc_16bpc);
1170 printf("dsc_all_bpp: %d\n",
1171 prxcap->dsc_all_bpp);
1172 printf("dsc_native_420: %d\n",
1173 prxcap->dsc_native_420);
1174 printf("dsc_1p2: %d\n",
1175 prxcap->dsc_1p2);
1176 printf("dsc_max_slices: 0x%x(%d slices)\n",
1177 prxcap->dsc_max_slices, dsc_max_slices_num[prxcap->dsc_max_slices]);
1178 printf("dsc_max_frl_rate: 0x%x\n",
1179 prxcap->dsc_max_frl_rate);
1180 printf("dsc_total_chunk_bytes: 0x%x\n",
1181 prxcap->dsc_total_chunk_bytes);
1182 if (prxcap->dv_info.ieeeoui == DOVI_IEEEOUI)
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001183 printf(" DolbyVision%d", prxcap->dv_info.ver);
xiang.wu114497ab2024-02-21 14:57:05 +08001184
1185 if (prxcap->hdr_info2.hdr_support)
1186 printf(" HDR/%d",
1187 prxcap->hdr_info2.hdr_support);
1188 if (prxcap->hdr_info.sbtm_info.sbtm_support)
1189 printf(" SBTM");
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001190 if (prxcap->dc_y444 || prxcap->dc_30bit || prxcap->dc_30bit_420)
1191 printf(" DeepColor");
1192 printf("\n");
xiang.wu114497ab2024-02-21 14:57:05 +08001193 printf("additional_vsif_num: %d\n", prxcap->additional_vsif_num);
1194 printf("ifdb_present: %d\n", prxcap->ifdb_present);
lizhi.hu506ddfa2024-07-10 21:35:41 +08001195 /*
1196 * for checkvalue which maybe used by application to adjust
xiang.wu114497ab2024-02-21 14:57:05 +08001197 * whether edid is changed
1198 */
1199 printf("checkvalue: %s\n", prxcap->hdmichecksum);
1200
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001201}
1202
1203static int do_info(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1204{
1205 struct hdmitx_dev *hdev = get_hdmitx21_device();
1206 struct hdmi_format_para *para;
1207
1208 if (!hdev) {
1209 pr_info("null hdmitx dev\n");
1210 return CMD_RET_FAILURE;
1211 }
1212 if (!hdev->para) {
1213 printf("null hdmitx para\n");
1214 return CMD_RET_FAILURE;
1215 }
1216
1217 para = hdev->para;
1218 printf("current mode %s vic %d\n", para->timing.name, hdev->vic);
1219 printf("cd%d cs%d cr%d\n", para->cd, para->cs, para->cr);
1220 printf("enc_idx %d\n", hdev->enc_idx);
1221 printf("frac_rate: %d\n", hdev->frac_rate_policy);
1222 printf("Rx EDID info\n");
1223 dump_full_edid(hdev->rawedid);
1224 disp_cap_show(hdev);
1225 vesa_cap_show(hdev);
1226 aud_cap_show(hdev);
1227 hdr_cap_show(hdev);
1228 dv_cap_show(hdev);
1229 dc_cap_show(hdev);
1230 edid_cap_show(hdev);
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001231 printf("dsc policy: %d, enable: %d\n", hdev->tx_common.tx_hw->hdmi_tx_cap.dsc_policy,
1232 para->dsc_en);
1233 printf("frl_rate: %d\n", hdev->para->frl_rate);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001234 return 1;
1235}
1236
1237static int xtochar(int num, char *checksum)
1238{
1239 struct hdmitx_dev *hdev = get_hdmitx21_device();
1240
1241 if (((hdev->rawedid[num] >> 4) & 0xf) <= 9)
1242 checksum[0] = ((hdev->rawedid[num] >> 4) & 0xf) + '0';
1243 else
1244 checksum[0] = ((hdev->rawedid[num] >> 4) & 0xf) - 10 + 'a';
1245
1246 if ((hdev->rawedid[num] & 0xf) <= 9)
1247 checksum[1] = (hdev->rawedid[num] & 0xf) + '0';
1248 else
1249 checksum[1] = (hdev->rawedid[num] & 0xf) - 10 + 'a';
1250
1251 return 0;
1252}
1253
lizhi.hu506ddfa2024-07-10 21:35:41 +08001254/*
1255 * hdr_priority definition:
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001256 * strategy1: bit[3:0]
1257 * 0: original cap
1258 * 1: disable dolby vision cap
1259 * 2: disable dolby vision and hdr/hlg cap
1260 * strategy2:
1261 * bit4: 1: disable dv 0:enable dv
1262 * bit5: 1: disable hdr10/hdr10+ 0: enable hdr10/hdr10+
1263 * bit6: 1: disable hlg 0: enable hlg
1264 * bit28-bit31 choose strategy: bit[31:28]
1265 * 0: strategy1
1266 * 1: strategy2
1267 */
1268
lizhi.hu506ddfa2024-07-10 21:35:41 +08001269/*
1270 * for uboot, there is no need to dynamically change the hdr_priority as
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001271 * kernel. So below functions only implement the disable_xxx_info() function,
1272 * and leave the enable_xxx_info as blank
1273 */
1274
1275/* dv_info */
1276static void enable_dv_info(struct dv_info *des, const struct dv_info *src)
1277{
1278 if (!des || !src)
1279 return;
1280}
1281
1282static void disable_dv_info(struct dv_info *des)
1283{
1284 if (!des)
1285 return;
1286
1287 memset(des, 0, sizeof(*des));
1288}
1289
1290/* hdr10 */
1291static void enable_hdr10_info(struct hdr_info *des, const struct hdr_info *src)
1292{
1293 if (!des || !src)
1294 return;
1295}
1296
1297static void disable_hdr10_info(struct hdr_info *des)
1298{
1299 if (!des)
1300 return;
1301
xiang.wu114497ab2024-02-21 14:57:05 +08001302 des->hdr_support = des->hdr_support & 0xB;
1303 des->static_metadata_type1 = 0;
1304 des->lumi_max = 0;
1305 des->lumi_avg = 0;
1306 des->lumi_min = 0;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001307}
1308
1309/* hdr10plus */
1310static void enable_hdr10p_info(struct hdr10_plus_info *des, const struct hdr10_plus_info *src)
1311{
1312 if (!des || !src)
1313 return;
1314}
1315
1316static void disable_hdr10p_info(struct hdr10_plus_info *des)
1317{
1318 if (!des)
1319 return;
1320
1321 memset(des, 0, sizeof(*des));
1322}
1323
1324/* hlg */
1325static void enable_hlg_info(struct hdr_info *des, const struct hdr_info *src)
1326{
1327 if (!des || !src)
1328 return;
1329}
1330
1331static void disable_hlg_info(struct hdr_info *des)
1332{
1333 if (!des)
1334 return;
1335
xiang.wu114497ab2024-02-21 14:57:05 +08001336 des->hdr_support = des->hdr_support & 0x7;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001337}
1338
1339static void enable_all_hdr_info(struct rx_cap *prxcap)
1340{
1341 if (!prxcap)
1342 return;
1343}
1344
1345static void update_hdr_strategy1(struct rx_cap *prxcap, u32 strategy)
1346{
1347 if (!prxcap)
1348 return;
1349
1350 switch (strategy) {
1351 case 0:
1352 enable_all_hdr_info(prxcap);
1353 break;
1354 case 1:
1355 disable_dv_info(&prxcap->dv_info);
1356 break;
1357 case 2:
1358 disable_dv_info(&prxcap->dv_info);
1359 disable_hdr10_info(&prxcap->hdr_info);
xiang.wu114497ab2024-02-21 14:57:05 +08001360 disable_hdr10p_info(&prxcap->hdr_info.hdr10plus_info);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001361 disable_hlg_info(&prxcap->hdr_info);
1362 break;
1363 default:
1364 break;
1365 }
1366}
1367
1368static void update_hdr_strategy2(struct rx_cap *prxcap, u32 strategy)
1369{
1370 if (!prxcap)
1371 return;
1372
1373 /* bit4: 1 disable dv 0 enable dv */
1374 if (strategy & BIT(4))
1375 disable_dv_info(&prxcap->dv_info);
1376 else
1377 enable_dv_info(&prxcap->dv_info, NULL);
1378 /* bit5: 1 disable hdr10/hdr10+ 0 enable hdr10/hdr10+ */
1379 if (strategy & BIT(5)) {
1380 disable_hdr10_info(&prxcap->hdr_info);
xiang.wu114497ab2024-02-21 14:57:05 +08001381 disable_hdr10p_info(&prxcap->hdr_info.hdr10plus_info);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001382 } else {
1383 enable_hdr10_info(&prxcap->hdr_info, NULL);
xiang.wu114497ab2024-02-21 14:57:05 +08001384 enable_hdr10p_info(&prxcap->hdr_info.hdr10plus_info, NULL);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001385 }
1386 /* bit6: 1 disable hlg 0 enable hlg */
1387 if (strategy & BIT(6))
1388 disable_hlg_info(&prxcap->hdr_info);
1389 else
1390 enable_hlg_info(&prxcap->hdr_info, NULL);
1391}
1392
1393static int hdmitx_set_hdr_priority(struct rx_cap *prxcap, u32 hdr_priority)
1394{
1395 u32 choose = 0;
1396 u32 strategy = 0;
1397
1398 if (!prxcap)
1399 return -1;
1400
1401 printf("%s, set hdr_prio: %u\n", __func__, hdr_priority);
1402 /* choose strategy: bit[31:28] */
1403 choose = (hdr_priority >> 28) & 0xf;
1404 switch (choose) {
1405 case 0:
1406 strategy = hdr_priority & 0xf;
1407 update_hdr_strategy1(prxcap, strategy);
1408 break;
1409 case 1:
1410 strategy = hdr_priority & 0xf0;
1411 update_hdr_strategy2(prxcap, strategy);
1412 break;
1413 default:
1414 break;
1415 }
1416 return 0;
1417}
1418
xiang.wu100ee50f2024-05-21 19:39:45 +08001419void hdmitx_update_dv_strategy_info(struct dv_info *dv)
1420{
1421 if (dv->ver == 0) {
1422 if (dv->length == 0x19)
1423 dv->support_DV_RGB_444_8BIT = 1;
1424 }
1425
1426 if (dv->ver == 1) {
1427 if (dv->length == 0x0B) {
1428 dv->support_DV_RGB_444_8BIT = 1;
1429 if (dv->low_latency == 0x01)
1430 dv->support_LL_YCbCr_422_12BIT = 1;
1431 } else if (dv->length == 0x0E) {
1432 dv->support_DV_RGB_444_8BIT = 1;
1433 }
1434 }
1435
1436 if (dv->ver == 2) {
1437 if (dv->length >= 0x0B) {
1438 if (dv->Interface != 0x00 && dv->Interface != 0x01)
1439 dv->support_DV_RGB_444_8BIT = 1;
1440 dv->support_LL_YCbCr_422_12BIT = 1;
1441 if (dv->Interface == 0x01 || dv->Interface == 0x03) {
1442 if (dv->sup_10b_12b_444 == 0x1)
1443 dv->support_LL_RGB_444_10BIT = 1;
1444 if (dv->sup_10b_12b_444 == 0x2)
1445 dv->support_LL_RGB_444_12BIT = 1;
1446 }
1447 }
1448 }
1449}
1450
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001451static void get_parse_edid_data(struct hdmitx_dev *hdev)
1452{
xiang.wu12a0497a2024-09-29 17:41:20 +08001453 int hdr_priority = get_hdr_strategy_priority();
1454
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001455 hdev->hwop.read_edid(hdev->rawedid);
1456
ruofei.zhao4a2ec0c2023-10-31 19:24:41 +08001457 /* dump edid raw data */
1458 dump_full_edid(hdev->rawedid);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001459
1460 /* parse edid data */
xiang.wu114497ab2024-02-21 14:57:05 +08001461 hdmitx_edid_parse(&hdev->RXCap, hdev->rawedid);
ruofei.zhao325a6542024-12-18 11:25:45 +08001462 hdmitx_cec_phy_addr_parse(&hdev->RXCap, hdev->rawedid);
1463 hdmitx_audio_parse(&hdev->RXCap, hdev->rawedid);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001464
xiang.wu100ee50f2024-05-21 19:39:45 +08001465 /* Update the member variables used by the dv running strategy */
1466 hdmitx_update_dv_strategy_info(&hdev->RXCap.dv_info);
1467 hdmitx_update_dv_strategy_info(&hdev->RXCap.dv_info2);
1468
xiang.wu12a0497a2024-09-29 17:41:20 +08001469 /*
1470 * For the first boot after burning, if the hdr_priority environment
1471 * variable is not configured, need to set it manually to avoid
1472 * the inconsistency between the value of the hdr_priority environment
1473 * variable and the result of the Google hdr policy during the boot
1474 * process, causing the TV to flash black.
xiang.wu1381f08d2024-11-04 14:43:56 +08001475 * AndroidU use strategy2: default DV priority
1476 * 268435456 = 0x10000000, DV priority.
1477 * If the DV library is not burned, the computer may flash black when
1478 * it is turned on for the first time after burning.
1479 * Linux Yocto not set.
xiang.wu12a0497a2024-09-29 17:41:20 +08001480 */
1481 if (hdr_priority == -1) {
xiang.wu1702bdd12024-10-22 16:24:40 +08001482#ifndef CONFIG_YOCTO
xiang.wu1381f08d2024-11-04 14:43:56 +08001483 hdr_priority = 268435456;
1484 env_set("hdr_priority", "268435456");
xiang.wu1702bdd12024-10-22 16:24:40 +08001485#endif
xiang.wu12a0497a2024-09-29 17:41:20 +08001486 }
1487
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001488 memcpy(&hdev->tx_common.rxcap, &hdev->RXCap, sizeof(hdev->tx_common.rxcap));
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001489}
1490
1491/* policy process: to find the output mode/attr/dv_type */
1492void scene_process(struct hdmitx_dev *hdev,
xiang.wu18cf0cd12024-06-13 15:27:52 +08001493 struct meson_policy_out *output)
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001494{
xiang.wu18cf0cd12024-06-13 15:27:52 +08001495 struct meson_policy_in input;
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001496
xiang.wu18cf0cd12024-06-13 15:27:52 +08001497 hdmitx_set_mode_policy();
1498 memset(&input, 0, sizeof(struct meson_policy_in));
1499 get_hdmi_input(hdev, &input);
1500 hdmitx_get_policy_output(output);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001501}
1502
1503static int do_get_parse_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1504{
1505 struct hdmitx_dev *hdev = get_hdmitx21_device();
1506 unsigned char *edid = hdev->rawedid;
1507 unsigned char *store_checkvalue;
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001508 unsigned int i;
1509 unsigned int checkvalue[4];
1510 unsigned int checkvalue1;
1511 unsigned int checkvalue2;
1512 char checksum[11];
1513 unsigned char def_cksum[] = {'0', 'x', '0', '0', '0', '0', '0', '0', '0', '0', '\0'};
1514 char *hdmimode;
1515 char *colorattribute;
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001516 int user_dv_mode;
1517 char *last_output_mode;
1518 char *last_colorattribute;
1519 int last_dv_status;
1520 bool over_write = false;
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001521 char dv_type[2] = {0};
xiang.wu18cf0cd12024-06-13 15:27:52 +08001522 struct meson_policy_out output;
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001523 struct hdmi_format_para *para = NULL;
1524 bool mode_support = false;
xiang.wu12a0497a2024-09-29 17:41:20 +08001525 int hdr_priority = get_hdr_strategy_priority();
lizhi.hu506ddfa2024-07-10 21:35:41 +08001526 /*
1527 * hdmi_mode / colorattribute may be null or "none".
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001528 * if either is null or "none", it means user not
1529 * selected manually, and need to select the best
1530 * mode or colorattribute by policy
1531 */
1532 bool no_manual_output = false;
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001533
zongdong.jiaob6fa9962024-08-25 19:51:48 +08001534 memset(edid, 0, EDID_BLK_SIZE * EDID_MAX_BLOCK);
1535
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001536 if (!hdev->hpd_state) {
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001537 printf("HDMI HPD low, no need parse EDID\n");
1538 return 1;
1539 }
xiang.wu18cf0cd12024-06-13 15:27:52 +08001540 memset(&output, 0, sizeof(struct meson_policy_out));
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001541
1542 get_parse_edid_data(hdev);
zongdong.jiao38b6b522024-11-20 14:47:56 +08001543 hdmitx_qms_map_vic(hdev);
zongdong.jiaob6fa9962024-08-25 19:51:48 +08001544 /*
1545 * QMS BRR selection
1546 * 120 or 60
1547 * TX cap & Rx Cap
1548 */
1549 if (0)
1550 qms_scene_pre_process(hdev);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001551
1552 /* check if the tv has changed or anything wrong */
1553 store_checkvalue = (unsigned char *)env_get("hdmichecksum");
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001554 /* get user selected output mode/color */
1555 colorattribute = env_get("user_colorattribute");
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001556 hdmimode = env_get("hdmimode");
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001557 user_dv_mode = get_ubootenv_dv_type();
1558
1559 last_output_mode = env_get("outputmode");
1560 last_colorattribute = env_get("colorattribute");
1561 last_dv_status = get_ubootenv_dv_status();
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001562 if (!store_checkvalue)
1563 store_checkvalue = def_cksum;
1564
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001565 printf("read hdmichecksum: %s, user hdmimode: %s, colorattribute: %s, dv_type: %d\n",
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001566 store_checkvalue, hdmimode ? hdmimode : "null",
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001567 colorattribute ? colorattribute : "null", user_dv_mode);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001568
1569 for (i = 0; i < 4; i++) {
1570 if (('0' <= store_checkvalue[i * 2 + 2]) && (store_checkvalue[i * 2 + 2] <= '9'))
1571 checkvalue1 = store_checkvalue[i * 2 + 2] - '0';
1572 else
1573 checkvalue1 = store_checkvalue[i * 2 + 2] - 'W';
1574 if (('0' <= store_checkvalue[i * 2 + 3]) && (store_checkvalue[i * 2 + 3] <= '9'))
1575 checkvalue2 = store_checkvalue[i * 2 + 3] - '0';
1576 else
1577 checkvalue2 = store_checkvalue[i * 2 + 3] - 'W';
1578 checkvalue[i] = checkvalue1 * 16 + checkvalue2;
1579 }
1580
1581 if (checkvalue[0] != hdev->rawedid[0x7f] ||
1582 checkvalue[1] != hdev->rawedid[0xff] ||
1583 checkvalue[2] != hdev->rawedid[0x17f] ||
1584 checkvalue[3] != hdev->rawedid[0x1ff]) {
1585 hdev->RXCap.edid_changed = 1;
1586
1587 checksum[0] = '0';
1588 checksum[1] = 'x';
1589 for (i = 0; i < 4; i++)
1590 xtochar(0x80 * i + 0x7f, &checksum[2 * i + 2]);
1591 checksum[10] = '\0';
xiang.wu114497ab2024-02-21 14:57:05 +08001592 memcpy(hdev->RXCap.hdmichecksum, checksum, 10);
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001593 printf("TV has changed, now crc: %s\n", checksum);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001594 } else {
xiang.wu114497ab2024-02-21 14:57:05 +08001595 memcpy(hdev->RXCap.hdmichecksum, store_checkvalue, 10);
1596 printf("TV is same, checksum: %s\n", hdev->RXCap.hdmichecksum);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001597 }
1598
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001599 /* check user have selected both mode/color or not */
1600 if (!hdmimode || !strcmp(hdmimode, "none") ||
1601 !colorattribute || !strcmp(colorattribute, "none"))
1602 no_manual_output = true;
1603 else
1604 no_manual_output = false;
1605
1606 if (!no_manual_output) {
1607 /* check current user selected mode + color support or not */
1608 para = hdmitx21_get_fmtpara(hdmimode, colorattribute);
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001609 if (!hdmitx_common_validate_format_para(&hdev->tx_common, para)) {
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001610 mode_support = true;
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001611 } else {
1612 printf("saved output mode not supported!\n");
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001613 mode_support = false;
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001614 }
1615
lizhi.hu506ddfa2024-07-10 21:35:41 +08001616 /*
1617 * if user selected mode/color/dv type which saved in ubootenv of
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001618 * hdmimode/user_colorattribute/user_prefer_dv_type are different
1619 * with last actual output mode/color/dv type which saved in
1620 * ubootenv of outputmode/colorattribute/dolby_status, then it means
1621 * that the user selected format is over-writen by policy(for example:
1622 * firstly user has selected HDR priority to HDR, and select color
1623 * to rgb,12bit(now the "user_colorattribute" env will be "rgb,12bit"),
1624 * but then it selected HDR priority to DV, the actual output color
1625 * will be "444,8bit" or "422,12bit" according to dv type, and
1626 * the ubootenv "colorattribute" will be "444,8bit" or "422,12bit"),
1627 * then uboot should use the policy to select the output format,
1628 * otherwise, uboot use hdmimode/user_colorattribute/user_prefer_dv_type
1629 * env, while system use outputmode/colorattribute/dolby_status env,
1630 * there will be always a mode change during bootup
1631 */
1632 if (mode_support) {
lizhi.hu506ddfa2024-07-10 21:35:41 +08001633 /*
1634 * note that for T7 multi-display, it may store panel in
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001635 * "outputmode" env, and will always run uboot policy
1636 */
1637 if (!last_output_mode || strcmp(hdmimode, last_output_mode))
1638 over_write = true;
1639 else if (!last_colorattribute ||
1640 strcmp(colorattribute, last_colorattribute))
1641 over_write = true;
1642 else if (user_dv_mode != last_dv_status)
1643 over_write = true;
1644 else
1645 over_write = false;
1646
1647 if (over_write)
1648 printf("last output_mode:%s, colorattribute:%s, dolby_status:%d\n",
1649 last_output_mode ? last_output_mode : "null",
1650 last_colorattribute ? last_colorattribute : "null",
1651 last_dv_status);
1652 }
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001653 }
lizhi.hu506ddfa2024-07-10 21:35:41 +08001654 /*
1655 * When outputting frl mode, if frl training fails under uboot,
xiang.wu1dba66a02024-05-28 19:53:01 +08001656 * in order to ensure that it is displayed under uboot, change
1657 * to the default TMDS mode for output display. systemctrl
1658 * maintains the original 8k policy. After the subsequent systermctrl
1659 * starts running, if it is checked that the current output is not the
1660 * original frl mode, it will switch to the original frl mode.
1661 */
1662 if (hdev->frl_train_fail_flag) {
1663 save_default_720p();
1664 } else if (hdev->RXCap.edid_changed || no_manual_output || !mode_support || over_write) {
lizhi.hu506ddfa2024-07-10 21:35:41 +08001665 /*
1666 * 4 cases need to decide output by uboot mode select policy:
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001667 * 1.TV changed
1668 * 2.either hdmimode or colorattribute is NULL or "none",
1669 * which means that user have not selected mode or colorattribute,
1670 * and need to select the auto best mode or best colorattribute.
1671 * 3.user selected mode not supportted by uboot (probably
1672 * means mode select policy or edid parse between sysctrl and
1673 * uboot have some gap), then need to find proper output mode
1674 * with uboot policy.
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001675 * 4.user selected mode is over writen by system policy
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001676 */
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001677 /* find proper mode if EDID changed */
xiang.wu18cf0cd12024-06-13 15:27:52 +08001678 scene_process(hdev, &output);
xiang.wu114497ab2024-02-21 14:57:05 +08001679 env_set("hdmichecksum", hdev->RXCap.hdmichecksum);
1680 if (hdmitx_edid_check_data_valid(0, hdev->rawedid)) {
lizhi.hu506ddfa2024-07-10 21:35:41 +08001681 /*
1682 * SWPL-34712: if EDID parsing error case, not save env,
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001683 * only output default mode(480p,RGB,8bit). after
1684 * EDID read OK, systemcontrol will recover the hdmi
1685 * mode from env, to avoid keep the default hdmi output
1686 */
xiang.wu18cf0cd12024-06-13 15:27:52 +08001687 memcpy(sel_hdmimode, output.displaymode,
1688 sizeof(output.displaymode));
lizhi.hu506ddfa2024-07-10 21:35:41 +08001689 /* The outputmode must be saved based on the value of connectorX_type. */
1690 if (env_get("connector0_type") &&
1691 is_valid_hdmi(env_get("connector0_type"))) {
1692 env_set("outputmode", output.displaymode);
1693 } else if (env_get("connector1_type") &&
1694 is_valid_hdmi(env_get("connector1_type"))) {
1695 env_set("outputmode2", output.displaymode);
1696 } else if (env_get("connector2_type") &&
1697 is_valid_hdmi(env_get("connector2_type"))) {
1698 env_set("outputmode3", output.displaymode);
1699 } else {
1700 pr_info("no config connectorX_type, save default %s outputmode\n",
xiang.wu18cf0cd12024-06-13 15:27:52 +08001701 output.displaymode);
lizhi.hu506ddfa2024-07-10 21:35:41 +08001702 env_set("outputmode", output.displaymode);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001703 }
1704 env_set("colorattribute",
xiang.wu18cf0cd12024-06-13 15:27:52 +08001705 output.deepcolor);
lizhi.hu506ddfa2024-07-10 21:35:41 +08001706 /*
1707 * if change from DV TV to HDR/SDR TV, don't change
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001708 * DV status to disabled, as DV core need to be enabled.
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001709 * that's to say connect DV TV & output DV-> power down box ->
1710 * connect HDR/SDR TV -> power on box, the dolby_status
1711 * will keep the same as that when connect DV TV under follow sink.
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001712 */
xiang.wu18cf0cd12024-06-13 15:27:52 +08001713 if (output.amdv_type != get_ubootenv_dv_status() &&
1714 output.amdv_type != DOLBY_VISION_DISABLE) {
1715 sprintf(dv_type, "%d", output.amdv_type);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001716 env_set("dolby_status", dv_type);
lizhi.hu506ddfa2024-07-10 21:35:41 +08001717 /*
1718 * according to the policy of systemcontrol,
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001719 * if current DV mode is not supported by TV
1720 * EDID, DV type maybe changed to one witch
1721 * TV support, and need VPP/DV module to
1722 * update new DV output mode.
1723 */
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001724 printf("update dolby_status: %d\n",
xiang.wu18cf0cd12024-06-13 15:27:52 +08001725 output.amdv_type);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001726 }
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001727 } else {
1728 save_default_720p();
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001729 }
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001730 printf("update outputmode: %s\n", sel_hdmimode);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001731 printf("update colorattribute: %s\n", env_get("colorattribute"));
1732 printf("update hdmichecksum: %s\n", env_get("hdmichecksum"));
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001733 } else {
1734 memset(sel_hdmimode, 0, sizeof(sel_hdmimode));
1735 memcpy(sel_hdmimode, hdmimode, strlen(hdmimode));
1736 if (is_hdmi_mode(env_get("outputmode")))
1737 env_set("outputmode", hdmimode);
1738 else if (is_hdmi_mode(env_get("outputmode2")))
1739 env_set("outputmode2", hdmimode);
1740 else if (is_hdmi_mode(env_get("outputmode3")))
1741 env_set("outputmode3", hdmimode);
1742 env_set("colorattribute", colorattribute);
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001743 }
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001744 env_set("save_outputmode", sel_hdmimode);
zongdong.jiaob6fa9962024-08-25 19:51:48 +08001745 /*
1746 * ubootenv dolby_status is used for is_dv_preference() decision,
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001747 * system_control save current dv output status in it.
1748 * it will be used by dv module later to decide DV output later.
1749 * if currently adaptive hdr, then we should set dolby_status to
1750 * 0, so that DV module won't enable DV.
1751 */
1752 if (get_hdr_policy() == 1)
1753 env_set("dolby_status", 0);
Wenjie Qiao389d3ea2023-05-25 16:07:03 +08001754 hdev->para = hdmitx21_get_fmtpara(sel_hdmimode, env_get("colorattribute"));
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001755 hdev->vic = hdev->para->timing.vic;
xiang.wu18cf0cd12024-06-13 15:27:52 +08001756
xiang.wu12a0497a2024-09-29 17:41:20 +08001757 /*
1758 * update the hdr/hdr10+/dv capabilities in the end of scene_process.
1759 * In order to be consistent with the HWC mode output policy, the real
1760 * capabilities of the TV need to be used when executing the uboot mode
1761 * policy. Finally, the corresponding hdr_cap/dv_cap needs to be blocked
1762 * based on hdr_priority.
1763 * eg: TV and BOX all support 1080p60hz DV, not support 1080p120hz DV, support HDR10, SDR
1764 * scene: UI choose 1080p120hz, always DV, reboot.
1765 * if update the hdr/hdr10+/dv capabilities before scene_process, uboot
1766 * scene_process executes sdr policy, but hwc executes hdr policy, Inconsistent
1767 * output modes lead to black flash
1768 */
xiang.wu18cf0cd12024-06-13 15:27:52 +08001769 if (hdr_priority != -1) {
1770 hdmitx_set_hdr_priority(&hdev->RXCap, hdr_priority);
1771 memcpy(&hdev->tx_common.rxcap, &hdev->RXCap, sizeof(hdev->tx_common.rxcap));
1772 }
1773
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001774 hdmitx_mask_rx_info(hdev);
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001775 hdev->para->frl_rate = hdmitx_select_frl_rate(&hdev->para->dsc_en,
1776 hdev->tx_common.tx_hw->hdmi_tx_cap.dsc_policy,
1777 hdev->para->vic, hdev->para->cs,
1778 hdev->para->cd);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001779 return 0;
1780}
1781
1782static int do_dsc_policy(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1783{
1784 struct hdmitx_dev *hdev = get_hdmitx21_device();
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001785 struct tx_cap *txcap = &hdev->tx_common.tx_hw->hdmi_tx_cap;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001786
1787 if (argc < 1)
1788 return cmd_usage(cmdtp);
1789
1790 if (strcmp(argv[1], "0") == 0)
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001791 txcap->dsc_policy = 0;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001792 else if (strcmp(argv[1], "1") == 0)
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001793 txcap->dsc_policy = 1;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001794 else if (strcmp(argv[1], "2") == 0)
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001795 txcap->dsc_policy = 2;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001796 else if (strcmp(argv[1], "3") == 0)
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001797 txcap->dsc_policy = 3;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001798 else if (strcmp(argv[1], "4") == 0)
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001799 txcap->dsc_policy = 4;
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001800 else
1801 printf("note: please set dsc policy as 0~4\n");
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001802 if (txcap->dsc_policy <= 4)
1803 printf("use dsc policy: %d\n", txcap->dsc_policy);
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001804
1805 return CMD_RET_SUCCESS;
1806}
1807
1808static int do_manual_frl_rate(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1809{
1810 struct hdmitx_dev *hdev = get_hdmitx21_device();
1811 unsigned int temp = 0;
1812 char *ptr;
1813
1814 /* if rx don't support FRL, return */
1815 if (!hdev->RXCap.max_frl_rate) {
1816 printf("rx not support FRL\n");
1817 return 0;
1818 }
1819
1820 temp = strtoul(argv[1], &ptr, 16);
1821 /* forced FRL rate setting */
1822 if (temp <= 6) {
1823 hdev->manual_frl_rate = temp;
1824 pr_info("force set frl_rate as %d\n", hdev->manual_frl_rate);
1825 } else {
1826 pr_info("error: should set frl_rate in 0 ~ 6\n");
1827 }
1828 if (hdev->manual_frl_rate > hdev->RXCap.max_frl_rate)
1829 pr_info("warning: larger than rx max_frl_rate %d\n", hdev->RXCap.max_frl_rate);
1830 return 0;
1831}
1832
1833static int do_manual_dfm_type(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1834{
1835 struct hdmitx_dev *hdev = get_hdmitx21_device();
1836 unsigned int temp = 0;
1837 char *ptr;
1838
1839 temp = strtoul(argv[1], &ptr, 10);
1840 /* forced dfm_type setting */
1841 if (temp <= 2) {
1842 hdev->dfm_type = temp;
1843 pr_info("force set dfm_type as %d\n", hdev->dfm_type);
1844 } else {
1845 pr_info("error: should set frl_rate in 0 ~ 2\n");
1846 }
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001847 return 0;
1848}
1849
Wenjie Qiao77833902023-12-18 19:01:59 +08001850#ifdef CONFIG_EFUSE_OBJ_API
1851static int do_efuse_show(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1852{
1853 struct hdmitx_dev *hdev = get_hdmitx21_device();
1854
1855 get_hdmi_efuse(hdev);
Wenjie Qiaoaf3ac882024-05-29 10:12:12 +08001856 pr_info("FEAT_DISABLE_HDMI_60HZ = %d\n", hdev->tx_common.efuse_dis_hdmi_4k60);
1857 pr_info("FEAT_DISABLE_OUTPUT_4K = %d\n", hdev->tx_common.efuse_dis_output_4k);
1858 pr_info("FEAT_DISABLE_HDCP_TX_22 = %d\n", hdev->tx_common.efuse_dis_hdcp_tx22);
1859 pr_info("FEAT_DISABLE_HDMI_TX_3D = %d\n", hdev->tx_common.efuse_dis_hdmi_tx3d);
1860 pr_info("FEAT_DISABLE_HDMI = %d\n", hdev->tx_common.efuse_dis_hdcp_tx14);
Wenjie Qiao77833902023-12-18 19:01:59 +08001861
1862 return 0;
1863}
1864#endif
1865
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001866static cmd_tbl_t cmd_hdmi_sub[] = {
1867 U_BOOT_CMD_MKENT(hpd, 1, 1, do_hpd_detect, "", ""),
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001868 U_BOOT_CMD_MKENT(rx_det, 1, 1, do_rx_det, "", ""),
1869 U_BOOT_CMD_MKENT(output, 3, 1, do_output, "", ""),
1870 U_BOOT_CMD_MKENT(clkmsr, 3, 1, do_clkmsr, "", ""),
1871 U_BOOT_CMD_MKENT(blank, 3, 1, do_blank, "", ""),
1872 U_BOOT_CMD_MKENT(off, 1, 1, do_off, "", ""),
1873 U_BOOT_CMD_MKENT(dump, 1, 1, do_dump, "", ""),
1874 U_BOOT_CMD_MKENT(info, 1, 1, do_info, "", ""),
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001875 U_BOOT_CMD_MKENT(reg, 3, 1, do_reg, "", ""),
1876 U_BOOT_CMD_MKENT(get_parse_edid, 1, 1, do_get_parse_edid, "", ""),
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001877 U_BOOT_CMD_MKENT(dsc_policy, 1, 1, do_dsc_policy, "", ""),
1878 U_BOOT_CMD_MKENT(frl_rate, 1, 1, do_manual_frl_rate, "", ""),
1879 U_BOOT_CMD_MKENT(dfm_type, 1, 1, do_manual_dfm_type, "", ""),
Wenjie Qiao77833902023-12-18 19:01:59 +08001880#ifdef CONFIG_EFUSE_OBJ_API
1881 U_BOOT_CMD_MKENT(efuse, 1, 1, do_efuse_show, "", ""),
1882#endif
xiang.wu1a6d6f1d2023-08-04 14:13:00 +08001883 U_BOOT_CMD_MKENT(pbist, 3, 1, do_pbist, "", ""),
1884 U_BOOT_CMD_MKENT(debug, 3, 1, do_debug, "", ""),
zhou.han89696e82024-12-26 11:38:28 +08001885 U_BOOT_CMD_MKENT(clk_analog_path, 3, 1, do_clk_path_config, "", ""),
xiang.wu114497ab2024-02-21 14:57:05 +08001886 U_BOOT_CMD_MKENT(get_rterm, 3, 1, get_rterm, "", ""),
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001887};
1888
1889static int do_hdmitx(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1890{
1891 cmd_tbl_t *c;
1892
1893 if (argc < 2)
1894 return cmd_usage(cmdtp);
1895
1896 argc--;
1897 argv++;
1898
1899 c = find_cmd_tbl(argv[0], &cmd_hdmi_sub[0], ARRAY_SIZE(cmd_hdmi_sub));
1900
1901 if (c)
1902 return c->cmd(cmdtp, flag, argc, argv);
1903 else
1904 return cmd_usage(cmdtp);
1905}
1906
1907U_BOOT_CMD(hdmitx, CONFIG_SYS_MAXARGS, 0, do_hdmitx,
1908 "HDMITX sub-system",
1909 "hdmitx version:20200618\n"
1910 "hdmitx hpd\n"
1911 " Detect hdmi rx plug-in\n"
Wenjie Qiao8a73a562023-02-23 18:37:14 +08001912 "hdmitx output [list | FORMAT | bist PATTERN]\n"
1913 " list: list support formats\n"
1914 " FORMAT can be 720p60/50hz, 1080i60/50hz, 1080p60hz, etc\n"
1915 " extend with 8bits/10bits, y444/y422/y420/rgb\n"
1916 " such as 2160p60hz,10bits,y420\n"
1917 " PATTERN: can be as: line, dot, off, or 1920(width)\n"
1918 "hdmitx blank [0|1]\n"
1919 " 1: output blank 0: output normal\n"
1920 "hdmitx clkmsr\n"
1921 " show hdmitx clocks\n"
1922 "hdmitx off\n"
1923 " Turn off hdmitx output\n"
1924 "hdmitx info\n"
1925 " current mode info\n"
1926 "hdmitx rx_det\n"
1927 " Auto detect if RX is FBC and set outputmode\n"
1928);
1929
1930struct hdr_info *hdmitx_get_rx_hdr_info(void)
1931{
1932 struct hdmitx_dev *hdev = get_hdmitx21_device();
1933
1934 return &hdev->RXCap.hdr_info;
1935}
Wenjie Qiao4bdbbee2024-02-01 10:16:44 +08001936
1937static int do_list_dsc_mode(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1938{
1939#ifdef CONFIG_AML_DSC_ENC
1940 dsc_enc_cap_show();
1941#endif
1942 return 0;
1943}
1944
1945static int do_dsc_debug(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1946{
1947#ifdef CONFIG_AML_DSC_ENC
1948 dsc_debug(argc - 1, argv + 1);
1949#endif
1950 return 0;
1951}
1952
1953static cmd_tbl_t cmd_dsc_sub[] = {
1954 U_BOOT_CMD_MKENT(list_mode, 1, 1, do_list_dsc_mode, "", ""),
1955 U_BOOT_CMD_MKENT(dbg, 20, 1, do_dsc_debug, "", ""),
1956};
1957
1958static int do_dsc_enc(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1959{
1960 cmd_tbl_t *c;
1961
1962 if (argc < 2)
1963 return cmd_usage(cmdtp);
1964
1965 argc--;
1966 argv++;
1967
1968 c = find_cmd_tbl(argv[0], &cmd_dsc_sub[0], ARRAY_SIZE(cmd_dsc_sub));
1969
1970 if (c)
1971 return c->cmd(cmdtp, flag, argc, argv);
1972 else
1973 return cmd_usage(cmdtp);
1974}
1975
1976U_BOOT_CMD(dsc, CONFIG_SYS_MAXARGS, 0, do_dsc_enc,
1977 "dsc cmd",
1978 "dsc help function\n"
1979 "dsc dbg state\n"
1980 " dump dsc status\n"
1981 "dsc dbg dump_reg\n"
1982 " dump dsc registers and venc registers\n"
1983 "dsc dbg read addr\n"
1984 " read dsc asic register\n"
1985 "dsc dbg write addr value\n"
1986 " write dsc asic register\n"
1987 "dsc dbg rst_dsc\n"
1988 " reset dsc enc\n"
1989 "dsc list_mode\n"
1990 " show supported dsc encode mode list\n"
1991);
1992